montedalrymple / yrv
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
☆17Updated 3 years ago
Alternatives and similar repositories for yrv:
Users that are interested in yrv are comparing it to the libraries listed below
- Reusable Verilog 2005 components for FPGA designs☆40Updated last year
- A small RISC-V core (SystemVerilog)☆31Updated 5 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated 2 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆26Updated 4 years ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- Wishbone interconnect utilities☆38Updated last week
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- IRSIM switch-level simulator for digital circuits☆31Updated 9 months ago
- A simple three-stage RISC-V CPU☆22Updated 3 years ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- The specification for the FIRRTL language☆51Updated this week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 2 months ago
- CMod-S6 SoC☆37Updated 7 years ago
- PicoRV☆44Updated 5 years ago
- A 6800 CPU written in nMigen☆49Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A Verilog Synthesis Regression Test☆35Updated 11 months ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆29Updated 4 years ago
- A reimplementation of a tiny stack CPU☆81Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago