montedalrymple / yrv
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
☆17Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for yrv
- SoftCPU/SoC engine-V☆54Updated last year
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- MR1 formally verified RISC-V CPU☆52Updated 5 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆45Updated this week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆25Updated this week
- A small RISC-V core (SystemVerilog)☆31Updated 5 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Documenting the Lattice ECP5 bit-stream format.☆51Updated last year
- Another tiny RISC-V implementation☆52Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- A reimplementation of a tiny stack CPU☆80Updated 11 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆89Updated 3 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- Wishbone interconnect utilities☆37Updated 5 months ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- RISC-V Dynamic Debugging Tool☆46Updated last year
- Optimized RISC-V FP emulation for 32-bit processors☆30Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆84Updated 5 years ago
- Another size-optimized RISC-V CPU for your consideration.☆47Updated this week
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- OpenRISC processor IP core based on Tomasulo algorithm☆29Updated 2 years ago
- Karnaugh Interactive Extendable ASIC Simulation Board AKA Karnix ASB-254☆14Updated 6 months ago