Alternatives and similar repositories for verif_elective_miet

Users that are interested in verif_elective_miet are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆36Updated this week
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆19Updated 6 months ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆19Updated 2 months ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated 7 months ago
• hurisson / pyuvm_primer
  Examples for using pyuvm
  ☆18Updated last year
• esynr3z / pyhdlsim
  Example of Python and PyTest powered workflow for a HDL simulation
  ☆15Updated 4 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated last month
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆38Updated last year
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆89Updated 2 months ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 6 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated this week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆48Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 3 weeks ago
• asicguy / spacex_uart
  Project and presentation for SpaceX Application
  ☆14Updated 7 years ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆42Updated 6 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆55Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• eine / hwd-ide
  ☆20Updated 5 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆61Updated 3 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆45Updated 9 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago