Alternatives and similar repositories for graywolf

Users that are interested in graywolf are comparing it to the libraries listed below

• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 3 weeks ago
• idea-fasoc / fasoc
  ☆56Updated 2 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆221Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 11 months ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆126Updated last week
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 3 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆149Updated 6 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆219Updated 2 weeks ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆65Updated 3 years ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆102Updated 3 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆169Updated 3 months ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆117Updated 4 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆144Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆209Updated this week
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆158Updated 7 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated this week
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆150Updated 3 weeks ago
• efabless / mpw_precheck
  ☆43Updated 9 months ago
• efabless / chipignite-resources
  ☆85Updated 3 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆59Updated 8 years ago