rubund / graywolfLinks
☆112Updated 4 years ago
Alternatives and similar repositories for graywolf
Users that are interested in graywolf are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 months ago
- Qrouter detail router for digital ASIC designs☆56Updated 5 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆217Updated 11 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- A utility for Composing FPGA designs from Peripherals☆184Updated 9 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆217Updated 3 weeks ago
- ☆56Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆122Updated 3 weeks ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- ADMS is a code generator for some of Verilog-A☆101Updated 2 years ago
- Fabric generator and CAD tools.☆198Updated last week
- A complete open-source design-for-testing (DFT) Solution☆164Updated last month
- Facilitates building open source tools for working with hardware description languages (HDLs)☆65Updated 5 years ago
- Mutation Cover with Yosys (MCY)☆87Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Yet Another RISC-V Implementation☆97Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆72Updated 3 weeks ago
- BAG framework☆41Updated last year
- ☆83Updated 2 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated 3 weeks ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆147Updated last month
- Open-source FPGA research and prototyping framework.☆208Updated last year
- Torc: Tools for Open Reconfigurable Computing☆39Updated 8 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated this week