rubund / graywolf
☆110Updated 4 years ago
Alternatives and similar repositories for graywolf:
Users that are interested in graywolf are comparing it to the libraries listed below
- FuseSoC standard core library☆129Updated 2 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆204Updated 5 months ago
- ☆53Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Qrouter detail router for digital ASIC designs☆56Updated 5 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆146Updated 4 months ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 5 years ago
- Fabric generator and CAD tools☆163Updated last month
- A utility for Composing FPGA designs from Peripherals☆173Updated 3 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆149Updated 7 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated 2 weeks ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆213Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 10 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆208Updated 4 months ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆114Updated 2 weeks ago
- Mutation Cover with Yosys (MCY)☆80Updated 2 weeks ago
- ☆77Updated last year
- FPGA tool performance profiling☆102Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆138Updated 2 years ago
- Yet Another RISC-V Implementation☆90Updated 6 months ago
- ☆79Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- SystemVerilog synthesis tool☆182Updated 2 weeks ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 3 years ago