rubund / graywolfLinks
☆113Updated 4 years ago
Alternatives and similar repositories for graywolf
Users that are interested in graywolf are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆135Updated 3 years ago
- FuseSoC standard core library☆139Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated 11 months ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- Qflow full end-to-end digital synthesis flow for ASIC designs☆212Updated 7 months ago
- Yet Another RISC-V Implementation☆93Updated 8 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆152Updated 7 years ago
- A utility for Composing FPGA designs from Peripherals☆179Updated 5 months ago
- ☆54Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆218Updated 2 weeks ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆117Updated 2 weeks ago
- A complete open-source design-for-testing (DFT) Solution☆153Updated this week
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆113Updated 3 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Fabric generator and CAD tools.☆185Updated this week
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 8 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆211Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆281Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- BAG framework☆40Updated 10 months ago
- ☆79Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- SystemVerilog synthesis tool☆194Updated 2 months ago