rubund / graywolfLinks
☆114Updated 4 years ago
Alternatives and similar repositories for graywolf
Users that are interested in graywolf are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆150Updated 2 weeks ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Updated 6 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated last year
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆126Updated last week
- ☆57Updated 2 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆159Updated 7 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆220Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Yet Another RISC-V Implementation☆99Updated last year
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆118Updated 4 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- A 32-bit RISC-V processor for mriscv project☆60Updated 8 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- ADMS is a code generator for some of Verilog-A☆103Updated 3 years ago
- BAG framework☆41Updated last year
- FPGA Assembly (FASM) Parser and Generator☆98Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Fabric generator and CAD tools.☆214Updated this week
- FPGA tool performance profiling☆104Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month