Alternatives and similar repositories for tatum

Users that are interested in tatum are comparing it to the libraries listed below

• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆93Updated 3 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆107Updated 8 months ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆56Updated 2 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆115Updated 4 years ago
• parallaxsw / OpenSTA
  ☆76Updated this week
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆89Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆59Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆97Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆171Updated last month
• aolofsson / POSH
  ☆44Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆51Updated 4 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 8 months ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆138Updated 9 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆161Updated last month
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 3 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last week
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 5 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated 2 months ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 7 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago