verilog-to-routing / tatumLinks
Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
☆61Updated last year
Alternatives and similar repositories for tatum
Users that are interested in tatum are comparing it to the libraries listed below
Sorting:
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- IDEA project source files☆106Updated 6 months ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- ☆105Updated 5 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Delay Calculation ToolKit☆31Updated 2 years ago
- ☆44Updated 5 years ago
- Introductory course into static timing analysis (STA).☆94Updated last month
- ☆70Updated this week
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆104Updated last year
- Qrouter detail router for digital ASIC designs☆57Updated last month
- EDA physical synthesis optimization kit☆57Updated last year
- UCSD Detailed Router☆87Updated 4 years ago
- ☆24Updated 4 years ago
- ☆33Updated 5 years ago
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆55Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Database and Tool Framework for EDA☆113Updated 4 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆95Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆177Updated 5 years ago
- A complete open-source design-for-testing (DFT) Solution☆153Updated last week
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆168Updated 2 weeks ago
- Framework Open EDA Gui☆65Updated 5 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- DATC RDF☆51Updated 4 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆44Updated 11 months ago