vaughnbetz / COFFELinks
☆43Updated 10 months ago
Alternatives and similar repositories for COFFE
Users that are interested in COFFE are comparing it to the libraries listed below
Sorting:
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆181Updated 5 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆47Updated last year
- An integrated CGRA design framework☆90Updated 4 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated last week
- ☆178Updated 4 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆127Updated 7 years ago
- ☆77Updated 10 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆173Updated this week
- Public release☆57Updated 5 years ago
- ☆60Updated 3 months ago
- Dataset for ML-guided Accelerator Design☆37Updated 8 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated last week
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 2 months ago
- Library of approximate arithmetic circuits☆55Updated 2 years ago
- ☆47Updated last month
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17Updated 9 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆23Updated 3 years ago
- ☆34Updated 6 years ago
- AIB Generator: Analog hardware compiler for AIB PHY☆34Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week