Alternatives and similar repositories for qtflow

Users that are interested in qtflow are comparing it to the libraries listed below

• rubund / graywolf
  ☆112Updated 4 years ago
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 3 months ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 3 months ago
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆56Updated 4 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated 11 months ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆69Updated last week
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 4 years ago
• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆34Updated last month
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• rochus-keller / VerilogCreator
  VerilogCreator is a QtCreator based IDE for Verilog 2005
  ☆173Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆46Updated 2 months ago
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆54Updated 3 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆23Updated 2 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆70Updated 3 years ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆100Updated 2 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆153Updated 7 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆182Updated 7 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated 3 weeks ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 9 years ago