Alternatives and similar repositories for qtflow

Users that are interested in qtflow are comparing it to the libraries listed below

• rubund / graywolf
  ☆114Updated 4 years ago
• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆58Updated 5 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆73Updated 4 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• rochus-keller / VerilogCreator
  VerilogCreator is a QtCreator based IDE for Verilog 2005
  ☆171Updated 3 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated this week
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• Qucs / ADMS
  ADMS is a code generator for some of Verilog-A
  ☆102Updated 3 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 6 years ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆75Updated this week
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆78Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• FOSSEE / nghdl
  This repository contain source code for ngspice and ghdl integration
  ☆33Updated 11 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆28Updated 2 weeks ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 2 years ago
• antonblanchard / microwatt-mpw1
  The 64 bit OpenPOWER Microwatt core, MPW1 tape out
  ☆16Updated 4 years ago