libresilicon / qtflowLinks
Free open source EDA tools
☆66Updated 5 years ago
Alternatives and similar repositories for qtflow
Users that are interested in qtflow are comparing it to the libraries listed below
Sorting:
- Copyleftist's Standard Cell Library☆99Updated last year
- ☆113Updated 4 years ago
- Magic VLSI Layout Tool☆21Updated 5 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 7 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- IRSIM switch-level simulator for digital circuits☆34Updated last month
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆51Updated last month
- OpenFPGA☆34Updated 7 years ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆117Updated 2 weeks ago
- Torc: Tools for Open Reconfigurable Computing☆38Updated 8 years ago
- BAG framework☆40Updated 10 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- ☆31Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 4 months ago
- ☆79Updated last year
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆61Updated last week
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆55Updated 4 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆80Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research☆38Updated 9 months ago
- Small footprint and configurable JESD204B core☆42Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago