Alternatives and similar repositories for qtflow

Users that are interested in qtflow are comparing it to the libraries listed below

• chipforge / StdCellLib
  Copyleftist's Standard Cell Library
  ☆99Updated last year
• rubund / graywolf
  ☆113Updated 4 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated last month
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆51Updated last month
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆69Updated 3 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆117Updated 2 weeks ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆38Updated 8 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 10 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 7 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated 4 months ago
• pieter3d / simview
  ☆79Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆61Updated last week
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆55Updated 4 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆80Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated 9 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago