Alternatives and similar repositories for cortex_m0_wrapper

Users that are interested in cortex_m0_wrapper are comparing it to the libraries listed below

• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• philippefaes / grlib
  ☆24Updated 11 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 4 months ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 3 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆18Updated 9 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• Digilent / Arty-A7-35-XADC
  ☆19Updated 4 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 10 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 10 years ago
• verilator / example-systemverilog
  ☆38Updated last year
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆18Updated 7 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 5 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆38Updated 3 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆36Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Updated 2 months ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆33Updated 10 years ago
• FPGANinjas / nitefury_pcie_xdma_ddr
  Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board
  ☆14Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated 2 weeks ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago