Alternatives and similar repositories for libsdcparse

Users that are interested in libsdcparse are comparing it to the libraries listed below

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated last month
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 3 weeks ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆23Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 10 months ago
• The-OpenROAD-Project-Attic / Resizer
  ☆15Updated 6 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆22Updated 3 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated this week
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆26Updated 5 months ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• iammituraj / fifo
  Synchronous FIFOs designed in Verilog/System Verilog.
  ☆24Updated last month
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆54Updated 2 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago