verilog-to-routing / libsdcparseLinks
☆12Updated 5 years ago
Alternatives and similar repositories for libsdcparse
Users that are interested in libsdcparse are comparing it to the libraries listed below
Sorting:
- Parsing library for BLIF netlists☆19Updated 9 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 9 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Extended and external tests for Verilator testing☆16Updated last week
- ☆33Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- ☆44Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- ☆18Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Open Source PHY v2☆29Updated last year
- Advanced Debug Interface☆15Updated 6 months ago
- Cross EDA Abstraction and Automation☆39Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ☆15Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆20Updated last year
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 11 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago
- LIS Network-on-Chip Implementation☆31Updated 8 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- YosysHQ SVA AXI Properties☆42Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago