FOSSEE / nghdlLinks
This repository contain source code for ngspice and ghdl integration
☆33Updated 9 months ago
Alternatives and similar repositories for nghdl
Users that are interested in nghdl are comparing it to the libraries listed below
Sorting:
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 4 months ago
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆35Updated 4 months ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆59Updated 2 months ago
- IRSIM switch-level simulator for digital circuits☆34Updated 6 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Coriolis VLSI EDA Tool (LIP6)☆72Updated 2 weeks ago
- ADMS is a code generator for some of Verilog-A☆101Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated last month
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆87Updated 10 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- An abstract language model of VHDL written in Python.☆57Updated this week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆30Updated 3 years ago
- A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, …☆46Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- BAG framework☆41Updated last year
- Raptor end-to-end FPGA Compiler and GUI☆87Updated 10 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- Framework Open EDA Gui☆69Updated 10 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆25Updated 3 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- Example of how to use UVM with Verilator☆23Updated this week
- XCircuit circuit drawing and schematic capture tool☆124Updated 6 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆55Updated last month
- Small footprint and configurable Inter-Chip communication cores☆65Updated last week
- System on Chip toolkit for Amaranth HDL☆95Updated last year
- A data acquisition framework in Python and Verilog.☆42Updated last week
- Sphinx Extension which generates various types of diagrams from Verilog code.☆62Updated 2 years ago
- Prefix tree adder space exploration library☆56Updated 11 months ago
- PicoRV☆43Updated 5 years ago