Alternatives and similar repositories for nghdl

Users that are interested in nghdl are comparing it to the libraries listed below

• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆34Updated this week
• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆51Updated 2 months ago
• 0x01be / rudder
  Learn, share and collaborate on ASIC design using open tools and technologies
  ☆13Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 11 months ago
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆68Updated last week
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated 5 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 7 months ago
• efabless / mpw_precheck
  ☆40Updated 4 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated 2 weeks ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last month
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 2 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆31Updated last month
• Xyce / Xyce_Regression
  The test suite for the Xyce Parallel Electronic Simulator
  ☆4Updated 3 weeks ago
• space-tudelft / cacd
  Space CACD
  ☆12Updated 5 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆43Updated 3 weeks ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆101Updated 4 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 4 months ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated this week
• pulp-platform / cheshire-ihp130-o
  ☆46Updated 2 months ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 4 years ago
• efabless / caravel_user_project_analog
  ☆47Updated 4 months ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago