FOSSEE / nghdl
This repository contain source code for ngspice and ghdl integration
☆30Updated 4 months ago
Alternatives and similar repositories for nghdl:
Users that are interested in nghdl are comparing it to the libraries listed below
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆47Updated last month
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆27Updated last month
- Small SERV-based SoC primarily for OpenMPW tapeout☆42Updated 4 months ago
- BAG framework☆40Updated 9 months ago
- IRSIM switch-level simulator for digital circuits☆33Updated last month
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆77Updated 4 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.☆23Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 5 months ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆59Updated this week
- Library of reusable VHDL components☆28Updated last year
- Coriolis VLSI EDA Tool (LIP6)☆65Updated this week
- ☆22Updated last year
- Automatic generation of real number models from analog circuits☆39Updated last year
- ☆45Updated 3 months ago
- An abstract language model of VHDL written in Python.☆52Updated this week
- A Verilog Synthesis Regression Test☆37Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Interchange formats for chip design.☆29Updated this week
- An automatic clock gating utility☆47Updated 3 weeks ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆13Updated 4 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆33Updated 3 years ago
- FuseSoc Verification Automation☆22Updated 2 years ago
- ☆36Updated 2 years ago
- SAR ADC on tiny tapeout☆38Updated 3 months ago
- Space CACD☆12Updated 5 years ago