FOSSEE / nghdl
This repository contain source code for ngspice and ghdl integration
☆28Updated last year
Related projects ⓘ
Alternatives and complementary repositories for nghdl
- BAG framework☆41Updated 3 months ago
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆70Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆30Updated 6 months ago
- An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.☆21Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆43Updated 3 months ago
- Automatic generation of real number models from analog circuits☆37Updated 7 months ago
- Hardware Description Library☆69Updated 2 months ago
- Filter builder tool☆17Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- Qrouter detail router for digital ASIC designs☆56Updated last month
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆41Updated 2 years ago
- Benchmarks for Yosys development☆21Updated 4 years ago
- A padring generator for ASICs☆22Updated last year
- Library of reusable VHDL components☆25Updated 8 months ago
- Virtual development board for HDL design☆39Updated last year
- A tiny Python package to parse spice raw data files.☆43Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆21Updated last year
- Generate symbols from HDL components/modules☆20Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆94Updated this week
- Coriolis VLSI EDA Tool (LIP6)☆54Updated this week
- ☆22Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆43Updated last year
- A framework for FPGA emulation of mixed-signal systems☆34Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆35Updated this week
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago