Alternatives and similar repositories for nghdl:

Users that are interested in nghdl are comparing it to the libraries listed below

• IHP-GmbH / IHP-Open-DesignLib
  Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
  ☆43Updated last week
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆62Updated last week
• wulffern / ciccreator
  Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…
  ☆27Updated last month
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• efabless / mpw_precheck
  ☆38Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆41Updated 4 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 4 months ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆38Updated last year
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated last week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• bluecheetah / bag
  BAG framework
  ☆40Updated 8 months ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆76Updated 4 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated this week
• space-tudelft / cacd
  Space CACD
  ☆12Updated 5 years ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆44Updated this week
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• aidangoettsch / asg
  An automatic schematic generation tool which generates schematics from a SPICE netlist, usually of output from qflow.
  ☆23Updated 4 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• NyanCAD / Mosaic
  A modern schematic entry and simulation program
  ☆68Updated last year
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆29Updated 3 weeks ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 3 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆38Updated 2 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆100Updated 2 months ago
• efabless / caravel_user_project_analog
  ☆45Updated 2 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated 2 years ago
• s-holst / GDS2WebGL
  Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.
  ☆54Updated 4 years ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆19Updated this week