Alternatives and similar repositories for EpicSim

Users that are interested in EpicSim are comparing it to the libraries listed below

• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆105Updated this week
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆97Updated 3 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 11 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• parallaxsw / OpenSTA
  ☆71Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated 3 weeks ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆69Updated last year
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆45Updated 10 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆102Updated 3 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆31Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated last week
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆101Updated last year
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆92Updated 3 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆82Updated 8 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 10 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated this week
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆75Updated 7 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆55Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆94Updated 3 weeks ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆87Updated 3 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago