eda-ricercatore / Modica-SRAMLinks
Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and charac…
☆16Updated 4 years ago
Alternatives and similar repositories for Modica-SRAM
Users that are interested in Modica-SRAM are comparing it to the libraries listed below
Sorting:
- Memory Compiler Tutorial☆13Updated 5 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆24Updated 3 years ago
- ☆44Updated last year
- Open source process design kit for 28nm open process☆66Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 6 months ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆71Updated 3 years ago
- ☆37Updated 6 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- SRAM☆22Updated 5 years ago
- ECE 5745 Tutorial 8: SRAM Generators☆15Updated 3 years ago
- Dataset for ML-guided Accelerator Design☆39Updated 11 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- EDA physical synthesis optimization kit☆62Updated last year
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated 2 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- A free standard cell library for SDDS-NCL circuits☆28Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆63Updated last week
- A repository for SystemC Learning examples☆71Updated 3 years ago
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆30Updated 4 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- ☆56Updated 6 years ago
- Project repo for the POSH on-chip network generator☆51Updated 7 months ago