Alternatives and similar repositories for FPGA-CAD-Framework

Users that are interested in FPGA-CAD-Framework are comparing it to the libraries listed below

• byuccl / tincr
  A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite
  ☆44Updated 6 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago
• intel / aib-phy-hardware
  ☆67Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• The-OpenROAD-Project-Attic / Resizer
  ☆15Updated 6 years ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆17Updated 6 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆65Updated 3 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 6 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆24Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated last year
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• idea-fasoc / fasoc
  ☆57Updated 2 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆70Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• sveditor / sveditor
  SystemVerilog Development Environment
  ☆54Updated 4 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 8 months ago