lnis-uofu / FreePDK45-RRAM-AddonLinks
A RRAM addon for the NCSU FreePDK 45nm
☆23Updated 3 years ago
Alternatives and similar repositories for FreePDK45-RRAM-Addon
Users that are interested in FreePDK45-RRAM-Addon are comparing it to the libraries listed below
Sorting:
- sram/rram/mram.. compiler☆39Updated last year
- Open source process design kit for 28nm open process☆60Updated last year
- SRAM☆22Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- ☆27Updated 5 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- A free standard cell library for SDDS-NCL circuits☆27Updated 2 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- ☆19Updated 11 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- ☆26Updated last year
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated last year
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 5 months ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆69Updated 2 years ago
- ☆42Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- NoC based MPSoC☆11Updated 11 years ago