lnis-uofu / FreePDK45-RRAM-Addon
A RRAM addon for the NCSU FreePDK 45nm
☆23Updated 3 years ago
Alternatives and similar repositories for FreePDK45-RRAM-Addon:
Users that are interested in FreePDK45-RRAM-Addon are comparing it to the libraries listed below
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆22Updated 3 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- ☆26Updated 5 years ago
- SRAM☆22Updated 4 years ago
- ECE 5745 Tutorial 8: SRAM Generators☆13Updated 3 years ago
- sram/rram/mram.. compiler☆33Updated last year
- The Verilog source code for DRUM approximate multiplier.☆30Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- A free standard cell library for SDDS-NCL circuits☆27Updated 2 years ago
- CNN accelerator☆28Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆65Updated 2 years ago
- Template for project1 TPU☆18Updated 3 years ago
- Open source process design kit for 28nm open process☆53Updated last year
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 7 years ago
- ☆31Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆24Updated 4 years ago
- ☆16Updated 2 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆14Updated 4 years ago
- Spiking Neural Network Accelerator☆15Updated 2 years ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆12Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆17Updated last year
- This is a tutorial on standard digital design flow☆75Updated 3 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last week