lnis-uofu / FreePDK45-RRAM-AddonLinks
A RRAM addon for the NCSU FreePDK 45nm
☆23Updated 3 years ago
Alternatives and similar repositories for FreePDK45-RRAM-Addon
Users that are interested in FreePDK45-RRAM-Addon are comparing it to the libraries listed below
Sorting:
- A free standard cell library for SDDS-NCL circuits☆27Updated 2 years ago
- Open source process design kit for 28nm open process☆59Updated last year
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- sram/rram/mram.. compiler☆37Updated last year
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- SRAM☆22Updated 4 years ago
- ☆27Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Updated 2 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 11 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 4 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- Approximate arithmetic circuits for FPGAs☆12Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- ☆41Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 2 weeks ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆19Updated 11 years ago
- NoC based MPSoC☆11Updated 11 years ago
- Intel's Analog Detailed Router☆39Updated 5 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago