drom / staLinks
🕒 Static Timing Analysis diagram renderer
☆13Updated last year
Alternatives and similar repositories for sta
Users that are interested in sta are comparing it to the libraries listed below
Sorting:
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- Cross EDA Abstraction and Automation☆39Updated 2 weeks ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- VHDL dependency analyzer☆24Updated 5 years ago
- Extended and external tests for Verilator testing☆16Updated this week
- ☆31Updated last year
- Advanced Debug Interface☆15Updated 7 months ago
- IP-XACT XML binding library☆16Updated 9 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- FuseSoc Verification Automation☆22Updated 3 years ago
- Digital Circuit rendering engine☆39Updated last month
- Python library for operations with VCD and other digital wave files☆52Updated 3 months ago
- ☆23Updated 4 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago
- SystemVerilog Linter based on pyslang☆31Updated 4 months ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- ☆17Updated 2 years ago
- SystemVerilog FSM generator☆32Updated last year
- Sphinx extension for visual documentation of hardware written in HWT☆11Updated 3 months ago
- Common SystemVerilog RTL modules for RgGen☆13Updated 2 weeks ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- Open Source PHY v2☆30Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated 2 weeks ago