Alternatives and similar repositories for sta:

Users that are interested in sta are comparing it to the libraries listed below

• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 5 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated 2 months ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆38Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆25Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 8 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆30Updated 10 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆31Updated 2 weeks ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 5 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆23Updated last month
• Nic30 / sphinx-hwt
  Sphinx extension for visual documentation of hardware written in HWT
  ☆11Updated 9 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated this week
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 4 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆37Updated 4 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆26Updated 11 months ago