🕒 Static Timing Analysis diagram renderer
☆13Dec 13, 2023Updated 2 years ago
Alternatives and similar repositories for sta
Users that are interested in sta are comparing it to the libraries listed below
Sorting:
- ☆17Apr 20, 2023Updated 2 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Nov 12, 2025Updated 3 months ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- Technology file parser in Rust☆13Apr 6, 2021Updated 4 years ago
- Collection of FreeCAD-OpenEMS-Export plugin projects for PCB Signal Integrity analysis.☆24Aug 30, 2025Updated 5 months ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS☆14Jan 30, 2024Updated 2 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 3 months ago
- Useful set of library functions for VHDL☆47Nov 24, 2013Updated 12 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- ☆15Apr 30, 2021Updated 4 years ago
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- OpenVC, an open source VHDL compiler/simulator☆20Oct 7, 2012Updated 13 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Mar 17, 2021Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Updated this week
- D3.js and ELK based schematic visualizer☆115Feb 27, 2024Updated 2 years ago
- Python scripts that help generating custom Sigasi Project and Libary configuration files☆19Feb 27, 2024Updated 2 years ago
- Object Notation for Markup Language☆23Jan 6, 2023Updated 3 years ago
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆20May 12, 2025Updated 9 months ago
- hardware library for hwt (= ipcore repo)☆44Dec 23, 2025Updated 2 months ago
- USB 1.1 Device IP Core☆21Oct 1, 2017Updated 8 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Simple parser for extracting VHDL documentation☆74Jul 12, 2024Updated last year
- ☆18Dec 15, 2022Updated 3 years ago
- A repository with all my custom symbols for KiCad☆23Dec 15, 2025Updated 2 months ago
- A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite☆44Oct 21, 2019Updated 6 years ago
- ChipTools is a utility to automate FPGA build and verification☆25Oct 22, 2021Updated 4 years ago
- VHDL dependency analyzer☆24Mar 10, 2020Updated 5 years ago
- use pivpi to drive testbench event☆21Jul 21, 2016Updated 9 years ago
- Exploration of alternative hardware description languages☆28Mar 9, 2018Updated 7 years ago
- Streaming based VHDL parser.☆84Jul 15, 2024Updated last year
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- ☆25Aug 7, 2023Updated 2 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆28Jul 27, 2018Updated 7 years ago
- A VHDL code generator for wallace tree multiplier☆10Apr 15, 2020Updated 5 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago