Alternatives and similar repositories for sta:

Users that are interested in sta are comparing it to the libraries listed below

• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆23Updated 4 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 10 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆14Updated 8 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆36Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 2 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆27Updated 8 months ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆17Updated 7 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆28Updated this week
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 3 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 3 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆29Updated this week
• edaa-org / pyEDAA.IPXACT
  An IP-XACT DOM for IEEE 1685-2014 in Python.
  ☆19Updated 2 weeks ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last month