paripath / cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
☆12Updated 4 years ago
Related projects: ⓘ
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆14Updated 6 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆20Updated 4 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- LibreSilicon's Standard Cell Library Generator☆14Updated 4 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Magic VLSI Layout Tool☆19Updated 4 years ago
- Benchmarks for Yosys development☆21Updated 4 years ago
- Open Source Detailed Placement engine☆11Updated 4 years ago
- 32-bit RISC-V microcontroller☆9Updated 3 years ago
- The source code that empowers OpenROAD Cloud☆11Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆38Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆21Updated last year
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆27Updated 3 weeks ago
- Provides a packaged collection of open source EDA tools☆12Updated 5 years ago
- ☆19Updated 2 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 3 years ago
- Open source EDA chip design flow☆42Updated 7 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆10Updated 10 years ago
- Cross EDA Abstraction and Automation☆33Updated last week
- ☆10Updated 3 years ago
- SRAM☆7Updated 4 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 4 years ago
- Open Source PHY v2☆23Updated 4 months ago
- Extended and external tests for Verilator testing☆14Updated last week
- tools regarding on analog modeling, validation, and generation☆18Updated last year
- Some simple examples for the Magic VLSI physical chip layout tool.☆27Updated 3 years ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆14Updated 3 years ago
- ☆23Updated 4 years ago
- Library of open source Process Design Kits (PDKs)☆21Updated this week
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆12Updated 7 years ago