Alternatives and similar repositories for cdf

Users that are interested in cdf are comparing it to the libraries listed below

• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆26Updated 2 months ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆18Updated 10 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆30Updated last year
• pradeepsk13 / vsdsram_sky130_1.8V
  Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node
  ☆13Updated 4 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆23Updated 5 years ago
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆19Updated 6 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆20Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 6 years ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 5 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆43Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• Deepak42074 / vsdsram_sky130
  Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns
  ☆13Updated 4 years ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated last week
• The-OpenROAD-Project-Attic / Resizer
  ☆15Updated 5 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• vsdip / vsdsram
  An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…
  ☆11Updated 5 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 5 months ago
• bluecheetah / cbag
  A C++ VLSI circuit schematic and layout database library
  ☆14Updated last year
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆51Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated last week
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆61Updated last year