jefftrull / EDASkelLinks
A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integration with the Qt event loop), a CMake build system, and a testing framework
☆39Updated 11 months ago
Alternatives and similar repositories for EDASkel
Users that are interested in EDASkel are comparing it to the libraries listed below
Sorting:
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- EpicSim Project☆71Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆57Updated 3 years ago
- Database and Tool Framework for EDA☆118Updated 4 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆100Updated 3 years ago
- Qrouter detail router for digital ASIC designs☆57Updated 6 months ago
- This library is a low level parser for the GDSII file format.☆36Updated 8 years ago
- Delay Calculation ToolKit☆32Updated 3 years ago
- Parsing library for BLIF netlists☆19Updated last year
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆44Updated 7 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆44Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 5 years ago
- C++ library and command-line utility for reading GDSII geometry files☆50Updated 4 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆127Updated 2 years ago
- UCSD Detailed Router☆91Updated 4 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- A simple C++ CMake project to jump-start development of SystemC models and systems☆28Updated 11 months ago
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆133Updated 6 years ago
- EDA physical synthesis optimization kit☆62Updated last year
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆236Updated this week
- VerilogCreator is a QtCreator based IDE for Verilog 2005☆171Updated 3 years ago
- ☆12Updated 5 years ago
- Framework Open EDA Gui☆69Updated 10 months ago
- liberty parser (For parsing IC timing lib file)☆65Updated 2 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆31Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆183Updated 5 months ago
- Global Router Built for ICCAD Contest 2019☆32Updated 5 years ago