Alternatives and similar repositories for EDASkel

Users that are interested in EDASkel are comparing it to the libraries listed below

• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• klayoutmatthias / dump_oas_gds2
  An OASIS and GDS2 (chip layout format) binary dump tool for debugging
  ☆41Updated 7 years ago
• EDDRSoftware / gdsFileParser
  This library is a low level parser for the GDSII file format.
  ☆35Updated 8 years ago
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆55Updated 2 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 2 months ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆97Updated 3 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆92Updated 3 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆115Updated 4 years ago
• x-epic / EpicSim
  EpicSim Project
  ☆70Updated 4 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• skuep / GDS3D
  Fork from https://sourceforge.net/projects/gds3d
  ☆68Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆58Updated last year
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• cibyr / lefdef
  Library Exchange Format (LEF) and Design Exchange Format (DEF)
  ☆19Updated 4 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 7 months ago
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆119Updated 2 years ago
• msoeken / alice
  C++ command shell library
  ☆53Updated 8 months ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆22Updated 6 years ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆56Updated 4 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆66Updated 6 months ago
• parallaxsw / OpenSTA
  ☆71Updated this week
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year