jefftrull / EDASkelLinks
A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integration with the Qt event loop), a CMake build system, and a testing framework
☆38Updated last year
Alternatives and similar repositories for EDASkel
Users that are interested in EDASkel are comparing it to the libraries listed below
Sorting:
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆63Updated last year
- This library is a low level parser for the GDSII file format.☆35Updated 8 years ago
- An OASIS and GDS2 (chip layout format) binary dump tool for debugging☆46Updated 8 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆59Updated 3 years ago
- Parsing library for BLIF netlists☆19Updated last year
- EpicSim Project☆71Updated 4 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Updated 2 years ago
- Qrouter detail router for digital ASIC designs☆57Updated 2 months ago
- Delay Calculation ToolKit☆32Updated 3 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Updated 3 years ago
- C++ library and command-line utility for reading GDSII geometry files☆52Updated 5 years ago
- Database and Tool Framework for EDA☆123Updated 5 years ago
- ☆44Updated 6 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆91Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆95Updated 6 years ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆32Updated 4 years ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆242Updated last week
- ☆12Updated 2 weeks ago
- Fork from https://sourceforge.net/projects/gds3d☆68Updated last year
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆59Updated 5 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆24Updated 5 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆127Updated 2 weeks ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- EDA physical synthesis optimization kit☆64Updated 2 years ago
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 5 years ago
- ☆33Updated 6 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14Updated 11 years ago
- A simple C++ CMake project to jump-start development of SystemC models and systems☆30Updated last year
- UCSD Detailed Router☆94Updated 5 years ago