OpenTimer / Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
☆50Updated 2 years ago
Related projects: ⓘ
- Delay Calculation ToolKit☆26Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆50Updated 4 years ago
- ☆28Updated 4 years ago
- ☆35Updated last week
- UCSD Detailed Router☆79Updated 3 years ago
- Intel's Analog Detailed Router☆37Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆29Updated 4 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆53Updated 3 months ago
- ☆37Updated 4 years ago
- Material for OpenROAD Tutorial at DAC 2020☆45Updated last year
- Bounded-Skew DME v1.3☆13Updated 6 years ago
- DATC Robust Design Flow.☆37Updated 4 years ago
- A Standalone Structural Verilog Parser☆79Updated 2 years ago
- Qrouter detail router for digital ASIC designs☆56Updated last year
- Circuit release of the MAGICAL project☆28Updated 4 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆20Updated 5 years ago
- ☆46Updated last month
- Database and Tool Framework for EDA☆101Updated 3 years ago
- IDEA project source files☆93Updated 2 weeks ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆140Updated 11 months ago
- VLSI EDA Global Router☆64Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆38Updated 4 years ago
- ☆34Updated 5 months ago
- Open Source Detailed Placement engine☆32Updated 4 years ago
- KLayout technology files for FreePDK45☆20Updated 3 years ago
- ☆17Updated last year
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆27Updated 9 years ago
- ☆19Updated 2 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆21Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆96Updated 6 months ago