OpenTimer / Parser-SPEF

Related projects ⓘ

Alternatives and complementary repositories for Parser-SPEF

• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆55Updated 5 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• aolofsson / IDEA
  ☆29Updated 4 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆34Updated 4 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 4 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆147Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆79Updated 3 years ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last month
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated last year
• The-OpenROAD-Project-Attic / OpenROAD-Utilities
  Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project
  ☆20Updated 5 years ago
• aolofsson / POSH
  ☆39Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆83Updated 2 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆98Updated last week
• purdue-onchip / gds2Para
  GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
  ☆114Updated last year
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆27Updated 9 years ago
• ABKGroup / RosettaStone
  ☆22Updated 2 years ago
• ABKGroup / PROBE3.0
  ☆36Updated 7 months ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆39Updated 4 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆29Updated 4 years ago
• Ravenslofty / librecell
  ☆19Updated 3 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 7 months ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago
• chipsalliance / aib-phy-generator
  AIB Generator: Analog hardware compiler for AIB PHY
  ☆30Updated 4 years ago
• eclufsc / libertyParser
  Mirror of Synopsys's Liberty parser library
  ☆18Updated 6 years ago