OpenTimer / Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
☆54Updated 2 years ago
Alternatives and similar repositories for Parser-SPEF:
Users that are interested in Parser-SPEF are comparing it to the libraries listed below
- ☆32Updated 5 years ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- Delay Calculation ToolKit☆27Updated 2 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 8 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆53Updated 4 years ago
- UCSD Detailed Router☆84Updated 4 years ago
- Open Source Detailed Placement engine☆36Updated 5 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆117Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆150Updated last month
- ☆37Updated 10 months ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- ☆23Updated 2 years ago
- A parallel global router using the Galois framework☆27Updated last year
- A Standalone Structural Verilog Parser☆86Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- EDA physical synthesis optimization kit☆50Updated last year
- ☆40Updated 5 years ago
- Qrouter detail router for digital ASIC designs☆56Updated 4 months ago
- Global Router Built for ICCAD Contest 2019☆30Updated 4 years ago
- Circuit release of the MAGICAL project☆31Updated 5 years ago
- VLSI EDA Global Router☆71Updated 7 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆98Updated 11 months ago
- ☆20Updated 3 years ago
- Mirror of Synopsys's Liberty parser library☆20Updated 6 years ago
- ☆56Updated this week
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- Collection of digital hardware modules & projects (benchmarks)☆41Updated 3 months ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- Automatic generation of real number models from analog circuits☆37Updated 10 months ago