OpenTimer / Parser-SPEFLinks
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
☆55Updated 2 years ago
Alternatives and similar repositories for Parser-SPEF
Users that are interested in Parser-SPEF are comparing it to the libraries listed below
Sorting:
- Delay Calculation ToolKit☆31Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆61Updated last year
- ☆33Updated 5 years ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- ☆44Updated 5 years ago
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- ☆24Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆55Updated 4 years ago
- ☆44Updated last year
- VLSI EDA Global Router☆73Updated 7 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Qrouter detail router for digital ASIC designs☆57Updated last month
- ☆20Updated 3 years ago
- Bounded-Skew DME v1.3☆14Updated 6 years ago
- EDA physical synthesis optimization kit☆57Updated last year
- Mirror of Synopsys's Liberty parser library☆21Updated 6 years ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- ☆70Updated this week
- Introductory course into static timing analysis (STA).☆94Updated last month
- DATC RDF☆51Updated 4 years ago
- A LEF/DEF Utility.☆30Updated 5 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- UCSD Detailed Router☆87Updated 4 years ago
- Circuit release of the MAGICAL project☆34Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆104Updated last year
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago