Alternatives and similar repositories for gate-sizing:

Users that are interested in gate-sizing are comparing it to the libraries listed below

• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆30Updated 5 years ago
• ABKGroup / RosettaStone
  ☆25Updated 2 years ago
• ABKGroup / TritonRoute-WXL
  ☆29Updated 4 years ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆35Updated 5 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆37Updated last year
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆72Updated 7 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆17Updated 3 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆54Updated 5 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆45Updated 3 months ago
• PKU-IDEA / SymDetect
  Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks
  ☆13Updated 2 years ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆21Updated 2 years ago
• UMN-EDA / BeGAN-benchmarks
  ☆24Updated last year
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆30Updated 3 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 3 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆37Updated 5 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 9 months ago
• digaryfa / UTH-Timer
  Gate-level timing estimation toolkit
  ☆22Updated 3 years ago
• recurme / Mixed-Cell-Height_legalizer
  ☆10Updated 8 months ago
• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆119Updated 4 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated this week
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆13Updated 2 years ago
• gaflach / usizer
  discrete gate sizing
  ☆13Updated 4 years ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆66Updated 5 months ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆28Updated 5 years ago
• NVlabs / Differentiable-Global-Router
  ☆17Updated 4 months ago