ultraembedded / riscv_socLinks
Basic RISC-V Test SoC
☆140Updated 6 years ago
Alternatives and similar repositories for riscv_soc
Users that are interested in riscv_soc are comparing it to the libraries listed below
Sorting:
- Verilog UART☆178Updated 12 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆106Updated 3 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆90Updated last week
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆217Updated 4 years ago
- A simple implementation of a UART modem in Verilog.☆151Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- RISC-V Verification Interface☆100Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆173Updated 9 months ago
- VeeR EL2 Core☆294Updated last week
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆133Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- Verilog digital signal processing components☆150Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆169Updated this week
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆99Updated last month
- Network on Chip Implementation written in SytemVerilog☆188Updated 2 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- ☆163Updated 2 years ago
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆132Updated this week
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆89Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- AHB3-Lite Interconnect☆90Updated last year
- SDRAM controller with AXI4 interface☆96Updated 6 years ago