ultraembedded / riscv_socLinks
Basic RISC-V Test SoC
☆162Updated 6 years ago
Alternatives and similar repositories for riscv_soc
Users that are interested in riscv_soc are comparing it to the libraries listed below
Sorting:
- Verilog UART☆187Updated 12 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆130Updated 2 months ago
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆85Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆279Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- ☆99Updated 4 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆142Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- A simple implementation of a UART modem in Verilog.☆168Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated 2 weeks ago
- Simple 8-bit UART realization on Verilog HDL.☆111Updated last year
- Verilog digital signal processing components☆162Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆255Updated 2 weeks ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆198Updated 3 months ago
- AHB3-Lite Interconnect☆107Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- RISC-V Verification Interface☆134Updated 2 weeks ago
- IEEE 754 floating point unit in Verilog☆150Updated 9 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆288Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- Verilog implementation of a RISC-V core☆133Updated 7 years ago
- VeeR EL2 Core☆309Updated last week
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆166Updated last year
- Verilog Configurable Cache☆187Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆178Updated this week