ultraembedded / riscv_soc
Basic RISC-V Test SoC
☆112Updated 5 years ago
Alternatives and similar repositories for riscv_soc:
Users that are interested in riscv_soc are comparing it to the libraries listed below
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- Verilog UART☆140Updated 11 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆133Updated last week
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆190Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆162Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 2 months ago
- RISC-V Verification Interface☆84Updated last week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆80Updated last year
- Network on Chip Implementation written in SytemVerilog☆168Updated 2 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆126Updated 5 years ago
- DDR2 memory controller written in Verilog☆73Updated 13 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Verilog digital signal processing components☆128Updated 2 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆304Updated 10 months ago
- A Fast, Low-Overhead On-chip Network☆175Updated this week
- PCI express simulation framework for Cocotb☆152Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆209Updated 4 years ago
- AHB3-Lite Interconnect☆84Updated 9 months ago
- ☆77Updated last month
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- ☆147Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆97Updated 10 months ago
- OpenXuantie - OpenE902 Core☆139Updated 8 months ago