Alternatives and similar repositories for riscv_soc

Users that are interested in riscv_soc are comparing it to the libraries listed below

• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆122Updated last month
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 3 weeks ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆110Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆128Updated 7 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆232Updated 2 weeks ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆138Updated 5 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated last month
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆78Updated last week
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆178Updated 2 months ago
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆61Updated last month
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆94Updated 6 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆148Updated 9 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆193Updated 3 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆112Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆149Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆278Updated 3 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆95Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago