ultraembedded / riscv_socLinks
Basic RISC-V Test SoC
☆138Updated 6 years ago
Alternatives and similar repositories for riscv_soc
Users that are interested in riscv_soc are comparing it to the libraries listed below
Sorting:
- Verilog UART☆177Updated 12 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- ☆89Updated this week
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆104Updated 2 months ago
- Verilog implementation of a RISC-V core☆122Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Simple 8-bit UART realization on Verilog HDL.☆108Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆272Updated 5 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- AHB3-Lite Interconnect☆90Updated last year
- Verilog digital signal processing components☆146Updated 2 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆171Updated 8 months ago
- SDRAM controller with AXI4 interface☆96Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆265Updated 3 months ago
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 2 weeks ago
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- Fixed Point Math Library for Verilog☆137Updated 11 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- VeeR EL2 Core☆292Updated 2 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- ☆240Updated 2 years ago
- RISC-V Verification Interface☆99Updated 2 months ago