Basic RISC-V Test SoC
☆176Apr 7, 2019Updated 6 years ago
Alternatives and similar repositories for riscv_soc
Users that are interested in riscv_soc are comparing it to the libraries listed below
Sorting:
- Various HDL (Verilog) IP Cores☆876Jul 1, 2021Updated 4 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- RISC-V CPU Core (RV32IM)☆1,656Sep 18, 2021Updated 4 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Mar 21, 2020Updated 5 years ago
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Feb 28, 2026Updated last week
- RISC-V System on Chip Template☆161Aug 18, 2025Updated 6 months ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆259Nov 6, 2024Updated last year
- This repository contains the design files of RISC-V Pipeline Core☆66May 11, 2023Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆569Oct 10, 2021Updated 4 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆181Jan 29, 2024Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- USB 2.0 FS Device controller IP core written in SystemVerilog☆39Dec 2, 2018Updated 7 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆26Dec 5, 2024Updated last year
- A simple implementation of a UART modem in Verilog.☆175Nov 10, 2021Updated 4 years ago
- ☆12Nov 11, 2015Updated 10 years ago
- ☆14Feb 23, 2026Updated last week
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- ☆20Feb 25, 2026Updated last week
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆60Jan 28, 2025Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆297Feb 4, 2026Updated last month
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68May 8, 2020Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆121Dec 17, 2023Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Nov 6, 2018Updated 7 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆225Jan 11, 2026Updated last month
- ☆14Feb 24, 2025Updated last year
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- An AXI4 crossbar implementation in SystemVerilog☆212Sep 2, 2025Updated 6 months ago
- AMBA bus generator including AXI, AHB, and APB☆119Jul 29, 2021Updated 4 years ago
- ☆93Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆128Jul 11, 2025Updated 7 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Jun 6, 2020Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆197Updated this week