Alternatives and similar repositories for riscv_soc:

Users that are interested in riscv_soc are comparing it to the libraries listed below

• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆99Updated 3 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆164Updated 4 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆113Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• jamieiles / uart
  Verilog UART
  ☆148Updated 11 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆87Updated 10 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆86Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆84Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆111Updated 10 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆91Updated 4 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆81Updated 2 weeks ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆140Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆76Updated 13 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆63Updated 3 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆62Updated 2 weeks ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆240Updated 5 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• raysalemi / Python4RTLVerification
  ☆152Updated 2 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆269Updated 2 weeks ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆196Updated last year