Alternatives and similar repositories for RISC-V-CPU

Users that are interested in RISC-V-CPU are comparing it to the libraries listed below

• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆170Updated this week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆174Updated 9 months ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆140Updated 6 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆90Updated 6 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆145Updated 9 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆221Updated 3 weeks ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆52Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆125Updated 10 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆104Updated last year
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆68Updated 8 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• psnjk / SimpleCache
  Simple cache design implementation in verilog
  ☆49Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆182Updated 5 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆108Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 8 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆96Updated last month
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆90Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆80Updated 3 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago