Alternatives and similar repositories for RISC-V-CPU

Users that are interested in RISC-V-CPU are comparing it to the libraries listed below

• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆212Updated 4 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆595Updated last year
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆136Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• RV-BOSC / OpenNoC
  ☆199Updated 4 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆466Updated 2 months ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆126Updated 10 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆168Updated 3 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆177Updated last month
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆148Updated 9 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆259Updated 3 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated 2 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆665Updated last month
• ucb-bar / berkeley-hardfloat
  ☆350Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆534Updated this week
• OSCPU / ysyxSoC
  ☆88Updated 3 weeks ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆215Updated 2 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆122Updated last year
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 5 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆679Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated 2 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆387Updated last month
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆309Updated last month
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆525Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆389Updated 4 months ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆327Updated 10 months ago
• OpenXiangShan / XS-Verilog-Library
  ☆44Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago