Alternatives and similar repositories for RISC-V-CPU

Users that are interested in RISC-V-CPU are comparing it to the libraries listed below

• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆214Updated 5 months ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆138Updated 5 years ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆598Updated last year
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆261Updated 3 years ago
• RV-BOSC / OpenNoC
  ☆204Updated 4 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆61Updated 3 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆169Updated 3 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆128Updated 10 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆468Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆300Updated 2 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆148Updated 9 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆178Updated 2 months ago
• ucb-bar / berkeley-hardfloat
  ☆354Updated 2 months ago
• chipsalliance / chisel-template
  A template project for beginning new Chisel work
  ☆670Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆539Updated 3 weeks ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆186Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆218Updated last week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆688Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆45Updated 3 years ago
• OSCPU / ysyxSoC
  ☆89Updated last month
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆317Updated last month
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 5 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆185Updated this week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆159Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆609Updated last month