RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
☆379Jan 12, 2018Updated 8 years ago
Alternatives and similar repositories for RISC-V-CPU
Users that are interested in RISC-V-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A MIPS CPU implemented in Verilog☆73Sep 12, 2017Updated 8 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆152Dec 2, 2019Updated 6 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 6 years ago
- RISC-V CPU Core (RV32IM)☆1,763Sep 18, 2021Updated 4 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆98Dec 5, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 6 years ago
- Pipelined RISC-V CPU☆28Jun 9, 2021Updated 5 years ago
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆214Jun 5, 2021Updated 5 years ago
- A simple RISC-V CPU written in Verilog.☆70Mar 16, 2026Updated 4 months ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,287Sep 18, 2021Updated 4 years ago
- 体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器☆90Nov 28, 2019Updated 6 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆177Nov 2, 2020Updated 5 years ago
- RISC-V RV32I CPU core☆36Mar 3, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆15Sep 27, 2022Updated 3 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆40Mar 25, 2020Updated 6 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,321Jul 31, 2026Updated last week
- fpga verilog risc-v rv32i cpu☆15Apr 18, 2023Updated 3 years ago
- ☆19May 11, 2020Updated 6 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆155Oct 2, 2025Updated 10 months ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆439Sep 14, 2023Updated 2 years ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆29Feb 19, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Basic RISC-V Test SoC☆206Apr 7, 2019Updated 7 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆133Dec 17, 2023Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,220Feb 11, 2026Updated 6 months ago
- A compiler for course Compiler 2019☆16Jan 9, 2020Updated 6 years ago
- A simple RISC V core for teaching☆211Jun 2, 2026Updated 2 months ago
- Learn and build GPU RTL from scratch☆22Aug 1, 2025Updated last year
- Verilog实现的简单五级流水线CPU，开发平台：Nexys3☆40Jul 9, 2015Updated 11 years ago
- The Ultra-Low Power RISC-V Core☆1,895Aug 6, 2025Updated last year
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,598May 12, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,062Updated this week
- 5-stage RISC-V CPU, originally developed for RISCBoy☆39Jul 1, 2023Updated 3 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 7 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆381Jul 12, 2017Updated 9 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆39Oct 29, 2023Updated 2 years ago