RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
☆352Jan 12, 2018Updated 8 years ago
Alternatives and similar repositories for RISC-V-CPU
Users that are interested in RISC-V-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆148Dec 2, 2019Updated 6 years ago
- A MIPS CPU implemented in Verilog☆70Sep 12, 2017Updated 8 years ago
- RISC-V-5 stage pipelined in verilog☆10Jul 24, 2020Updated 5 years ago
- RISC-V CPU Core (RV32IM)☆1,668Sep 18, 2021Updated 4 years ago
- A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL☆95Dec 5, 2019Updated 6 years ago
- 基于RISC_V32I指令集架构的五级流水CPU☆15Sep 30, 2019Updated 6 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- A simple RISC-V CPU written in Verilog.☆72Mar 16, 2026Updated last week
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- 5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.☆214Jun 5, 2021Updated 4 years ago
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆160Nov 2, 2020Updated 5 years ago
- RISC-V RV32I CPU core☆34Mar 3, 2023Updated 3 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆36Mar 25, 2020Updated 5 years ago
- ☆14Sep 27, 2022Updated 3 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆88Nov 28, 2019Updated 6 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- Basic RISC-V Test SoC☆180Apr 7, 2019Updated 6 years ago
- ☆19May 11, 2020Updated 5 years ago
- An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。☆433Sep 14, 2023Updated 2 years ago
- fpga verilog risc-v rv32i cpu☆14Apr 18, 2023Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆121Dec 17, 2023Updated 2 years ago
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆16Jan 4, 2020Updated 6 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- A compiler for course Compiler 2019☆16Jan 9, 2020Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,075Feb 11, 2026Updated last month
- Learn and build GPU RTL from scratch☆20Aug 1, 2025Updated 7 months ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆12Apr 18, 2024Updated last year
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆24Feb 19, 2025Updated last year
- Verilog实现的简单五级流水线CPU,开发平台:Nexys3☆40Jul 9, 2015Updated 10 years ago
- A simple RISC V core for teaching☆201Dec 30, 2021Updated 4 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆36Jul 1, 2023Updated 2 years ago
- The Ultra-Low Power RISC-V Core☆1,774Aug 6, 2025Updated 7 months ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,501Jan 7, 2026Updated 2 months ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 7 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Updated this week
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 6 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆372Jul 12, 2017Updated 8 years ago
- A 5 stage-pipeline RV32I implementation in VHDL☆22Mar 13, 2020Updated 6 years ago