chipsalliance / rocket-chip-fpga-shellsLinks
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
☆19Updated 8 months ago
Alternatives and similar repositories for rocket-chip-fpga-shells
Users that are interested in rocket-chip-fpga-shells are comparing it to the libraries listed below
Sorting:
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- Run Rocket Chip on VCU128☆30Updated 8 months ago
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 4 months ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- Open-source non-blocking L2 cache☆46Updated last week
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆30Updated 5 months ago
- Wrapper for ETH Ariane Core☆20Updated 4 months ago
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- ☆14Updated last week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 6 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆18Updated 8 months ago
- Synthesisable SIMT-style RISC-V GPGPU☆40Updated 3 weeks ago
- CV32E40X Design-Verification environment☆12Updated last year
- ☆15Updated 2 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Updated 6 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A Hardware Pipeline Description Language☆45Updated 3 weeks ago
- A coverage library for Chisel designs☆11Updated 5 years ago
- Open-source high-performance non-blocking cache☆87Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆14Updated 2 months ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆34Updated 3 months ago
- ☆40Updated last month
- chipyard in mill :P☆78Updated last year
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆16Updated 5 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated last week
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆30Updated 4 years ago
- What if everything is a io_uring?☆16Updated 2 years ago