chipsalliance / rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
☆17Updated 4 months ago
Alternatives and similar repositories for rocket-chip-fpga-shells:
Users that are interested in rocket-chip-fpga-shells are comparing it to the libraries listed below
- RTL blocks compatible with the Rocket Chip Generator☆14Updated 9 months ago
- Wrappers for open source FPU hardware implementations.☆30Updated 11 months ago
- Wrapper for ETH Ariane Core☆19Updated 2 weeks ago
- Run Rocket Chip on VCU128☆29Updated 4 months ago
- Open-source non-blocking L2 cache☆37Updated this week
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 10 months ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A Rocket-based RISC-V superscalar in-order core☆31Updated last week
- Useful utilities for BAR projects☆31Updated last year
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆28Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆25Updated 2 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆27Updated last month
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 4 years ago
- ☆28Updated 3 months ago
- A Rocket-Chip with a Dynamically Randomized LLC☆12Updated 6 months ago
- ☆38Updated last year
- CV32E40X Design-Verification environment☆12Updated last year
- ☆32Updated last week
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated last year
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- A DMA Controller for RISCV CPUs☆14Updated 9 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆13Updated last week
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- The 'missing header' for Chisel☆18Updated last week
- This repo includes XiangShan's function units☆18Updated this week
- Simple UVM environment for experimenting with Verilator.☆19Updated 2 months ago