Alternatives and similar repositories for rocket-chip-fpga-shells

Users that are interested in rocket-chip-fpga-shells are comparing it to the libraries listed below

• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 weeks ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 7 months ago
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆32Updated 9 months ago
• CTSRD-CHERI / garnet
  Amazon F1-inspired Xilinx VCU118 hardware design framework
  ☆12Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆21Updated 2 months ago
• OpenXiangShan / Utility
  ☆15Updated 3 weeks ago
• efeslab / moesi-prime
  ☆15Updated 2 years ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆31Updated 2 months ago
• ucb-bar / AuRORA
  Virtualized Accelerator Orchestration for Multi-Tenant Workloads
  ☆19Updated 11 months ago
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆15Updated last year
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆15Updated 5 months ago
• pulp-platform / hci
  Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
  ☆14Updated this week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 4 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆35Updated last month
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• jjyy-Huang / SpinalHDL-ethernet
  ☆20Updated 2 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last month
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆43Updated 4 months ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• CMU-SAFARI / Pythia-HDL
  Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …
  ☆17Updated 4 years ago
• iscas-tis / CHA
  ☆19Updated last year
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 8 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆106Updated last month