riscv-boom / boom-templateLinks
DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM
☆37Updated 6 years ago
Alternatives and similar repositories for boom-template
Users that are interested in boom-template are comparing it to the libraries listed below
Sorting:
- ☆82Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆64Updated 2 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Public release☆58Updated 6 years ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated last week
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated 2 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆146Updated last year
- educational microarchitectures for risc-v isa☆67Updated 6 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- ☆88Updated 3 years ago
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- An open-source UCIe implementation☆82Updated last week
- A dynamic verification library for Chisel.☆160Updated last year
- ☆82Updated 11 years ago
- Chisel components for FPGA projects☆128Updated 2 years ago
- ☆71Updated 5 years ago
- ☆101Updated 5 months ago
- ☆66Updated 3 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- Network on Chip Implementation written in SytemVerilog☆197Updated 3 years ago
- Project repo for the POSH on-chip network generator☆52Updated 10 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 5 years ago
- ☆193Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year