Martoni / spi2wbLinks
Drive a Wishbone master bus with an SPI bus.
☆11Updated 6 months ago
Alternatives and similar repositories for spi2wb
Users that are interested in spi2wb are comparing it to the libraries listed below
Sorting:
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Library of reusable VHDL components☆28Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- Specification of the Wishbone SoC Interconnect Architecture☆48Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆24Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated this week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆30Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Updated last year
- Wishbone interconnect utilities☆43Updated 8 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆36Updated last week
- USB virtual model in C++ for Verilog☆32Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago
- ☆33Updated 2 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago
- UART cocotb module☆11Updated 4 years ago
- demo project to show how to use vivado tcl scripts to do everything.☆17Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆35Updated 8 months ago
- An open-source HDL register code generator fast enough to run in real time.☆74Updated this week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 8 months ago
- ☆26Updated 6 months ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago