ucb-bar / berkeley-testfloat-3

Related projects ⓘ

Alternatives and complementary repositories for berkeley-testfloat-3

• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆105Updated 2 years ago
• etherzhhb / Shang
  The Shang high-level synthesis framework
  ☆119Updated 10 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆45Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆107Updated 3 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated 3 weeks ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆33Updated 2 years ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆139Updated 4 months ago
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 8 months ago
• rdaly525 / coreir
  ☆101Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆161Updated 3 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆79Updated this week
• riscv-software-src / riscof
  ☆64Updated 3 weeks ago
• bsc-loca / sargantana
  ☆76Updated 6 months ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆24Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆36Updated last month
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆135Updated 2 weeks ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆90Updated 2 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆29Updated last month
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆92Updated 7 months ago
• BSVLang / Main
  Main page
  ☆126Updated 4 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆119Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆28Updated 2 weeks ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆85Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆79Updated 7 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆64Updated 5 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆78Updated last month