ucb-bar / berkeley-testfloat-3Links
TestFloat release 3
☆73Updated 10 months ago
Alternatives and similar repositories for berkeley-testfloat-3
Users that are interested in berkeley-testfloat-3 are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Updated 8 months ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Testing processors with Random Instruction Generation☆52Updated 3 weeks ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆153Updated 3 weeks ago
- Open-source high-performance non-blocking cache☆92Updated 2 months ago
- ☆61Updated 5 years ago
- ☆51Updated 3 weeks ago
- Open-source non-blocking L2 cache☆52Updated this week
- The specification for the FIRRTL language☆62Updated 3 weeks ago
- RISC-V Packed SIMD Extension☆157Updated last week
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 6 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Documentation for the BOOM processor☆47Updated 8 years ago
- ☆89Updated 5 months ago
- ☆148Updated last year
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 2 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 4 months ago
- The multi-core cluster of a PULP system.☆111Updated this week
- Open source high performance IEEE-754 floating unit☆89Updated last year
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆141Updated last week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 3 months ago
- PACoGen: Posit Arithmetic Core Generator☆76Updated 6 years ago
- RISC-V architecture concurrency model litmus tests☆99Updated 2 weeks ago
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago