Alternatives and similar repositories for berkeley-testfloat-3

Users that are interested in berkeley-testfloat-3 are comparing it to the libraries listed below

• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆180Updated 7 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆166Updated 5 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆44Updated 5 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 3 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆151Updated last month
• riscv / riscv-bfloat16
  ☆38Updated last year
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 5 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆121Updated 2 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated 2 weeks ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆152Updated last month
• riscvarchive / riscv-CMOs
  ☆89Updated 3 months ago
• pulp-platform / redmule
  ☆88Updated 2 weeks ago
• riscv / riscv-test-env
  ☆51Updated 2 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆136Updated 3 weeks ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 2 months ago
• j-marjanovic / chisel-stuff
  Various examples for Chisel HDL
  ☆29Updated 3 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆107Updated 3 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 2 months ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆87Updated 2 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆109Updated last month
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆45Updated 8 months ago
• rdaly525 / coreir
  ☆104Updated 3 years ago