Alternatives and similar repositories for berkeley-testfloat-3:

Users that are interested in berkeley-testfloat-3 are comparing it to the libraries listed below

• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆130Updated 3 weeks ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆52Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆88Updated last month
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆155Updated 4 years ago
• ucb-bar / sha3
  ☆78Updated last year
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆35Updated 3 years ago
• riscv / riscv-test-env
  ☆45Updated 3 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• riscv / riscv-bfloat16
  ☆33Updated 8 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆91Updated 2 years ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆62Updated 7 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆69Updated 5 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆83Updated 2 weeks ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆60Updated 4 months ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 5 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 3 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆78Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• tenstorrent / rv-core-dv-kit
  ☆24Updated last month
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 8 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago