Alternatives and similar repositories for berkeley-testfloat-3

Users that are interested in berkeley-testfloat-3 are comparing it to the libraries listed below

• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆169Updated 5 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last week
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆138Updated last month
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆114Updated 2 years ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 5 months ago
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆155Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆171Updated 2 weeks ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆127Updated last year
• riscvarchive / riscv-CMOs
  ☆89Updated 4 months ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆87Updated 3 months ago
• tenstorrent / rv-core-dv-kit
  ☆29Updated 10 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆108Updated 3 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆50Updated this week
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆176Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last month
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆48Updated 6 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆96Updated this week
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 2 weeks ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆69Updated 11 months ago