ucb-bar / berkeley-testfloat-3Links
TestFloat release 3
☆71Updated 9 months ago
Alternatives and similar repositories for berkeley-testfloat-3
Users that are interested in berkeley-testfloat-3 are comparing it to the libraries listed below
Sorting:
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 4 months ago
- RiscyOO: RISC-V Out-of-Order Processor☆168Updated 5 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆137Updated last month
- The specification for the FIRRTL language☆62Updated 3 weeks ago
- ☆61Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- Chisel RISC-V Vector 1.0 Implementation☆124Updated 2 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- RISC-V Packed SIMD Extension☆154Updated last month
- ☆51Updated 3 months ago
- ☆89Updated 4 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 7 months ago
- Open-source non-blocking L2 cache☆51Updated this week
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- A libgloss replacement for RISC-V that supports HTIF☆42Updated last year
- Synthesisable SIMT-style RISC-V GPGPU☆48Updated 5 months ago
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- ☆121Updated 4 months ago
- ☆89Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- The Shang high-level synthesis framework☆120Updated 11 years ago
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- ☆38Updated last year
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- The multi-core cluster of a PULP system.☆110Updated last month
- ☆28Updated 9 months ago
- Run Rocket Chip on VCU128☆30Updated 2 months ago