Alternatives and similar repositories for hardposit-chisel3

Users that are interested in hardposit-chisel3 are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆64Updated 8 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆144Updated last month
• Kuree / kratos
  Debuggable hardware generator
  ☆69Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated 2 weeks ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• rdaly525 / coreir
  ☆103Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆33Updated 2 months ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆58Updated last week
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆45Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆101Updated 5 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆73Updated 5 years ago
• pulp-platform / redmule
  ☆68Updated this week
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆166Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 2 months ago
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆63Updated 5 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated last week
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆32Updated 10 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated 3 weeks ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated 3 weeks ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 3 years ago