thoughtworks / hardposit-chisel3Links
Chisel library for Unum Type-III Posit Arithmetic
☆39Updated 4 months ago
Alternatives and similar repositories for hardposit-chisel3
Users that are interested in hardposit-chisel3 are comparing it to the libraries listed below
Sorting:
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- PACoGen: Posit Arithmetic Core Generator☆74Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- Debuggable hardware generator☆69Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆145Updated 2 months ago
- The specification for the FIRRTL language☆59Updated last week
- A polyhedral compiler for hardware accelerators☆59Updated last year
- ☆56Updated 3 years ago
- ☆103Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- Visual Simulation of Register Transfer Logic☆99Updated 5 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 2 months ago
- A Rocket-based RISC-V superscalar in-order core☆34Updated 3 months ago
- A Hardware Pipeline Description Language☆45Updated 3 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 3 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- high-performance RTL simulator☆168Updated last year
- ☆71Updated last week
- Next generation CGRA generator☆112Updated last week
- DASS HLS Compiler☆29Updated last year
- Floating point modules for CHISEL☆32Updated 10 years ago
- A vector processor implemented in Chisel☆21Updated 10 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 9 months ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆23Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- A configurable SRAM generator☆53Updated 3 weeks ago