thoughtworks / hardposit-chisel3Links
Chisel library for Unum Type-III Posit Arithmetic
☆45Updated 8 months ago
Alternatives and similar repositories for hardposit-chisel3
Users that are interested in hardposit-chisel3 are comparing it to the libraries listed below
Sorting:
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- ☆58Updated 3 years ago
- Open-Source Posit RISC-V Core with Quire Capability☆68Updated 10 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- The specification for the FIRRTL language☆62Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Debuggable hardware generator☆70Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆88Updated 2 weeks ago
- high-performance RTL simulator☆184Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- ☆87Updated last year
- A Rocket-based RISC-V superscalar in-order core☆36Updated 2 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated 3 months ago
- Visual Simulation of Register Transfer Logic☆107Updated 3 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated last month
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- ☆104Updated 3 years ago
- Chisel Cheatsheet☆34Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- FPGA tool performance profiling☆103Updated last year
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆24Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- ☆15Updated 4 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week