ucb-bar / block-inclusivecache-sifive
☆11Updated 3 years ago
Alternatives and similar repositories for block-inclusivecache-sifive:
Users that are interested in block-inclusivecache-sifive are comparing it to the libraries listed below
- ☆77Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated this week
- Pure digital components of a UCIe controller☆51Updated this week
- Open source high performance IEEE-754 floating unit☆67Updated 10 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆35Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆22Updated 2 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- ☆57Updated last month
- ☆25Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 4 months ago
- ☆77Updated 10 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆49Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆47Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆54Updated last month
- Advanced Architecture Labs with CVA6☆54Updated last year
- eyeriss-chisel3☆40Updated 2 years ago
- ☆40Updated 5 years ago
- ☆25Updated 4 years ago
- A Scala library for Context-Dependent Environments☆47Updated 8 months ago
- ☆50Updated 3 years ago
- Scripts for XiangShan☆13Updated last week
- YSYX RISC-V Project NJU Study Group☆13Updated 2 weeks ago
- Generic Register Interface (contains various adapters)☆103Updated 3 months ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆47Updated 5 months ago
- Basic floating-point components for RISC-V processors☆63Updated 5 years ago
- ☆32Updated 3 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆53Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆35Updated this week