johan92 / verilog-coding-style

Related projects: ⓘ

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆30Updated 3 weeks ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆41Updated 3 weeks ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 3 years ago
• hypernyan / eth_vlg
  ☆51Updated 2 years ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆23Updated 5 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆51Updated last year
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆66Updated 4 months ago
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆28Updated 5 years ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆62Updated this week
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆72Updated last year
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆150Updated 11 months ago
• Des333 / soc-fpga2sdram-test
  Testing FPGA2SDRAM interface on Altera Cyclone V SoC
  ☆13Updated 9 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆103Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆75Updated 4 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆106Updated 8 months ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆75Updated last year
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆37Updated 3 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆84Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆20Updated 3 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆46Updated 2 years ago
• jomonkjoy / Tri-Mode-Ethernet-MAC-10-100-1000-
  Ethernet-MAC System verilog
  ☆10Updated 6 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆53Updated last year
• CospanDesign / nysa-sata
  ☆79Updated 7 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆49Updated 4 years ago
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆23Updated 6 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆96Updated last month
• poucotm / SublimeLinter-contrib-verilator
  👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)
  ☆14Updated 2 months ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆38Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆105Updated last month