Verilog (SystemVerilog) coding style
☆42Jan 7, 2019Updated 7 years ago
Alternatives and similar repositories for verilog-coding-style
Users that are interested in verilog-coding-style are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- River Raid game on FPGA☆23Oct 30, 2016Updated 10 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 6 months ago
- Hardware CD/CI and Development Containers 🚢☆11Jul 20, 2022Updated 4 years ago
- ☆50Nov 9, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A small RISC-V core (SystemVerilog)☆33Aug 26, 2019Updated 7 years ago
- Control and Status Register map generator for HDL projects☆149May 24, 2025Updated last year
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 9 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Testing FPGA2SDRAM interface on Altera Cyclone V SoC☆14May 12, 2015Updated 11 years ago
- Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.☆1,250Apr 21, 2026Updated 6 months ago
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆186Oct 28, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- cgit docker container☆16Jul 13, 2021Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Sep 5, 2015Updated 11 years ago
- Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs☆18Dec 7, 2017Updated 8 years ago
- Standalone OpenOCD and CMSIS-SVD based peripheral register viewer written on Python☆37Jan 14, 2019Updated 7 years ago
- A Python package for creating and solving constrained randomization problems.☆20Oct 16, 2026Updated 2 weeks ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆19Oct 23, 2016Updated 10 years ago
- Repository gathering basic modules for CDC purpose☆64Dec 31, 2019Updated 6 years ago
- ☆29Jan 18, 2021Updated 5 years ago
- Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…☆105Jan 12, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Open source implementation of a Verilog formatter☆187Jan 27, 2022Updated 4 years ago
- Simple library to interface with Hitachi-compatible character LCDs for the Sipeed Tang Nano 4K Gowin FPGA board.☆10Aug 13, 2022Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆62Feb 25, 2023Updated 3 years ago
- playing with XOR video patterns on an FPGA☆13Apr 19, 2021Updated 5 years ago
- Port of https://github.com/eleqian/WiDSO/tree/master/MCU/USB-Blaster to GCC and "traditional" STM32F103C8T6 Bluepill board.☆45Feb 15, 2019Updated 7 years ago
- ☆14Feb 18, 2021Updated 5 years ago
- 10 Gbit/s flexible and extensible Ethernet FPGA-based traffic generator☆11Oct 3, 2014Updated 12 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 4 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- UVM interactive debug library☆34Feb 28, 2026Updated 8 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated last year
- HTTP proxy with kerberos authentication similar to cntlm project☆12Oct 20, 2025Updated last year
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 6 years ago
- Computer Architecture course's project Fall 2018, Innopolis University.☆10Dec 6, 2018Updated 7 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆136Feb 11, 2021Updated 5 years ago
- Solving Sudokus using open source formal verification tools☆18Aug 16, 2022Updated 4 years ago