Alternatives and similar repositories for verilog-coding-style

Users that are interested in verilog-coding-style are comparing it to the libraries listed below

• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆36Updated this week
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆88Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆12Updated 10 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆89Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆19Updated 2 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆73Updated 7 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 5 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• CospanDesign / nysa-sata
  ☆85Updated 8 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆19Updated 6 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 5 years ago
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆32Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆63Updated 2 years ago
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆48Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago