Alternatives and similar repositories for pyvcd

Users that are interested in pyvcd are comparing it to the libraries listed below

• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆108Updated 2 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆61Updated last week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 3 weeks ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated this week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated 2 weeks ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 4 months ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆232Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆78Updated last week
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated 11 months ago
• kevinpt / symbolator
  HDL symbol generator
  ☆194Updated 2 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 9 months ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆65Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated last week
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• pieter3d / simview
  ☆86Updated last week
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆63Updated 8 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 4 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 4 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆117Updated last week
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 3 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated this week