Alternatives and similar repositories for Pyverilog:

Users that are interested in Pyverilog are comparing it to the libraries listed below

• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,233Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆669Updated last week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆289Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆523Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆790Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆601Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆559Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆414Updated 2 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆405Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆754Updated 3 years ago
• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆310Updated 7 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆578Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆400Updated 6 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated this week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,075Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆860Updated last year
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆697Updated this week
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆516Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated 2 weeks ago
• alexforencich / verilog-axi
  Verilog AXI components for FPGA implementation
  ☆1,648Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆460Updated last month
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆315Updated 10 months ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆563Updated 7 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆423Updated 3 years ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆881Updated 4 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,917Updated this week
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆415Updated 2 years ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆518Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆431Updated this week