Alternatives and similar repositories for Pyverilog

Users that are interested in Pyverilog are comparing it to the libraries listed below

• pyuvm / pyuvm
  The UVM written in Python
  ☆440Updated this week
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,321Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆587Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆645Updated 3 weeks ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆657Updated 2 years ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆298Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆699Updated last month
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆812Updated 4 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,025Updated this week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆625Updated 3 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆920Updated 2 weeks ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆431Updated 2 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆556Updated 3 years ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,116Updated last week
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆455Updated this week
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆486Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆332Updated last week
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆426Updated 2 years ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆587Updated 7 years ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆783Updated 2 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆398Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆510Updated 5 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆503Updated 7 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,136Updated last month
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆419Updated 2 months ago
• PyHDI / veriloggen
  Veriloggen: A Mixed-Paradigm Hardware Construction Framework
  ☆320Updated 11 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆403Updated last month