Verdi like, verilog code signal trace and show hierarchy script
☆19Oct 16, 2019Updated 6 years ago
Alternatives and similar repositories for vtags
Users that are interested in vtags are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆17Jun 5, 2024Updated 2 years ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 11 years ago
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement☆29Updated this week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆13Aug 22, 2022Updated 4 years ago
- VLSI CAD Algorithm Visualizations implemented as Java Applications☆18Aug 23, 2023Updated 3 years ago
- Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.☆290Aug 31, 2026Updated last week
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- wavedrom to verilog converter☆18Sep 14, 2021Updated 4 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆36Apr 15, 2020Updated 6 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- e300 and u500 devkits☆10Nov 15, 2020Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 2 months ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 10 years ago
- General purpose task runner☆12Nov 10, 2025Updated 9 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- ☆10Jun 11, 2016Updated 10 years ago
- AXI X-Bar☆20Apr 8, 2020Updated 6 years ago
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- USB 1.1 PHY☆11Jul 17, 2014Updated 12 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Prototype firmware for 3d printers on an STM32F4xxx☆10Feb 26, 2021Updated 5 years ago
- high-performance RTL simulator☆195Aug 4, 2026Updated last month
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated 2 years ago
- Xilinx Modifications to Halide☆13May 3, 2021Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆71Feb 13, 2025Updated last year
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆15Dec 22, 2025Updated 8 months ago
- Virtual Platform for AWS FPGA support☆16Oct 19, 2018Updated 7 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- Live preview by any shell command while editing☆15Dec 15, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 4 years ago
- ☆137Nov 17, 2025Updated 9 months ago
- Converts GDSII (IC layout database) files to SVG (Vector graphics) files.☆17Feb 10, 2023Updated 3 years ago
- math learning notes in orgmode☆13Aug 5, 2016Updated 10 years ago
- Graph accelerator on FPGAs and ASICs☆11Aug 16, 2018Updated 8 years ago
- Common SystemVerilog components☆793Updated this week
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago