SystemVerilog syntax highlight/indent support in vim
☆52Jul 10, 2024Updated last year
Alternatives and similar repositories for vim-SystemVerilog
Users that are interested in vim-SystemVerilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog/SystemVerilog Syntax and Omni-completion☆414Oct 13, 2024Updated last year
- verilog filetype plugin to enable emacs verilog-mode autos☆25Apr 24, 2022Updated 3 years ago
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- Jude's vimrc for DV work(fine tuning for SV/UVM)☆21Mar 12, 2024Updated 2 years ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆10Mar 18, 2020Updated 6 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Apr 1, 2026Updated 2 weeks ago
- ☆10Apr 8, 2021Updated 5 years ago
- Download proccedings from DVCon☆24Mar 29, 2026Updated 3 weeks ago
- Contains commonly used UVM components (agents, environments and tests).☆33Aug 17, 2018Updated 7 years ago
- SystemVerilog Development Environment☆54Sep 9, 2021Updated 4 years ago
- How to design a MIPI CSI interface with Efinix Trion FPGA T20F169 QUICKLY☆10Feb 6, 2020Updated 6 years ago
- ☆26Aug 10, 2023Updated 2 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆134Nov 29, 2017Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 11 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- UVM AHB VIP☆97Sep 13, 2025Updated 7 months ago
- ☆37Mar 3, 2016Updated 10 years ago
- SystemVerilog vim scripts☆68Jan 25, 2023Updated 3 years ago
- UVM VIP architecture generator☆21Aug 24, 2020Updated 5 years ago
- ☆15Jun 27, 2024Updated last year
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL☆70Updated this week
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- highlighting match of matchit.vim☆18May 4, 2014Updated 11 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- Basic Common Modules☆47Mar 18, 2026Updated last month
- UVM interactive debug library☆35Feb 28, 2026Updated last month
- ☆12May 31, 2016Updated 9 years ago
- [deprecated]use mshr-h/vscode-verilog-hdl-support☆24Nov 3, 2018Updated 7 years ago
- uvm AXI BFM(bus functional model)☆267Jun 23, 2013Updated 12 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- An UVM example of UART☆19Aug 31, 2020Updated 5 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- USB 1.1 Host and Function IP core☆26Jul 17, 2014Updated 11 years ago
- APB Logic☆24Feb 24, 2026Updated last month
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago