Alternatives and similar repositories for vim-SystemVerilog

Users that are interested in vim-SystemVerilog are comparing it to the libraries listed below

• zhuzhzh / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆25Updated 3 years ago
• nachumk / systemverilog.vim
  SystemVerilog vim scripts
  ☆70Updated 3 years ago
• jmcneal / verilog-support
  Edit SystemVerilog files (and UVM files) in Vim/gVim
  ☆30Updated last year
• vhda / verilog_systemverilog.vim
  Verilog/SystemVerilog Syntax and Omni-completion
  ☆413Updated last year
• zhajio1988 / my_vimrc
  Jude's vimrc for DV work(fine tuning for SV/UVM)
  ☆21Updated last year
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆35Updated 8 years ago
• hjking / uvm_gen
  UVM Generator
  ☆50Updated last year
• emwzq / example_uvm
  UVM实战随书源码
  ☆57Updated 7 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated last year
• vim-scripts / verilog_emacsauto.vim
  verilog filetype plugin to enable emacs verilog-mode autos
  ☆17Updated 3 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆87Updated 4 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆86Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆78Updated 5 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆79Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆160Updated 7 years ago
• advanced-uvm / second_edition
  Code for the second edition of Advanced UVM.
  ☆32Updated 9 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆156Updated 7 months ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆57Updated 9 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆149Updated 4 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆42Updated 6 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆145Updated 2 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆53Updated 10 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆44Updated 3 years ago
• tenthousandfailures / constraintlayering
  SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples
  ☆17Updated 10 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆86Updated 4 years ago
• accellera / uvm
  ☆60Updated 9 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆74Updated 6 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆265Updated 12 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆93Updated 4 months ago