🇯 JSON encoder and decoder in pure SystemVerilog
☆16Jul 7, 2024Updated 2 years ago
Alternatives and similar repositories for svjson
Users that are interested in svjson are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Control and Status Register map generator for HDL projects☆147May 24, 2025Updated last year
- Sample of project using UIO(User Space IO) Interrupt(ZYBO/Linux/PUMP_AXI4).☆13Nov 26, 2017Updated 8 years ago
- A Python package for creating and solving constrained randomization problems.☆19Aug 10, 2026Updated 3 weeks ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- HTB_Write_Ups☆27Feb 25, 2024Updated 2 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 4 months ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆27Mar 5, 2025Updated last year
- Dockerfile for ModelSim Version 16 GUI☆15Aug 16, 2021Updated 5 years ago
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- ☆225Aug 16, 2026Updated 2 weeks ago
- Mastering FPGASIC Book☆19Oct 26, 2025Updated 10 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- PSSGen: Portable Test and Stimulus Standard DSL Generator☆15Jun 30, 2026Updated 2 months ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆148Updated this week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆82Oct 22, 2024Updated last year
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- Contains examples to start with Kactus2.☆25Aug 5, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆22Sep 26, 2025Updated 11 months ago
- Architecting and Building High Speed SoCs, published by Packt☆32Jan 18, 2023Updated 3 years ago
- ☆29Jan 18, 2021Updated 5 years ago
- ☆19Jun 2, 2025Updated last year
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 2 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Jan 28, 2026Updated 7 months ago
- Web-based HDL diagramming tool☆86May 1, 2023Updated 3 years ago
- ☆13Jul 20, 2026Updated last month
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Репозиторий канала Verification For All☆15May 27, 2026Updated 3 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- A SystemVerilog language server based on the Slang library.☆310Updated this week
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- CMake based hardware build system☆44Updated this week
- ☆44Mar 9, 2026Updated 5 months ago
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago