kactus2 / kactus2devLinks
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
☆243Updated this week
Alternatives and similar repositories for kactus2dev
Users that are interested in kactus2dev are comparing it to the libraries listed below
Sorting:
- SystemRDL 2.0 language compiler front-end☆269Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆206Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆243Updated 4 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆312Updated 6 months ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Updated 3 weeks ago
- Control and status register code generator toolchain☆165Updated last month
- UVM 1.2 port to Python☆257Updated 11 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆435Updated 4 months ago
- ☆208Updated 10 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆118Updated 3 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆135Updated 2 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆284Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆145Updated last week
- Unit testing for cocotb☆165Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- Build Customized FPGA Implementations for Vivado☆354Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week
- SystemC/TLM-2.0 Co-simulation framework☆264Updated 7 months ago
- Python-based IP-XACT parser and utilities☆142Updated last year
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆300Updated last week
- ☆174Updated 3 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- PCI express simulation framework for Cocotb☆186Updated 4 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆127Updated last week
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆73Updated last week
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- HDL symbol generator☆200Updated 2 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Updated 3 years ago
- RISC-V Verification Interface☆136Updated last month
- A complete open-source design-for-testing (DFT) Solution☆176Updated 4 months ago