kactus2 / kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
☆205Updated this week
Alternatives and similar repositories for kactus2dev:
Users that are interested in kactus2dev are comparing it to the libraries listed below
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆199Updated 5 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated last month
- Control and status register code generator toolchain☆122Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆312Updated this week
- UVM 1.2 port to Python☆250Updated 2 months ago
- SystemRDL 2.0 language compiler front-end☆250Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆387Updated 2 weeks ago
- ☆198Updated last month
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆125Updated last year
- ☆152Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated 2 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 3 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆289Updated last month
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆111Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆209Updated 4 months ago
- RISC-V Verification Interface☆87Updated last month
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆57Updated 3 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- Code generation tool for control and status registers☆379Updated last month
- SystemC/TLM-2.0 Co-simulation framework☆242Updated 5 months ago
- FuseSoC standard core library☆132Updated last week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated this week
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆77Updated 5 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Fabric generator and CAD tools☆164Updated last week
- PCI express simulation framework for Cocotb☆157Updated last year
- Code used in☆181Updated 7 years ago
- The UVM written in Python☆421Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆272Updated last week