Kactus2 is a graphical EDA tool based on the IP-XACT standard.
☆248Mar 13, 2026Updated last week
Alternatives and similar repositories for kactus2dev
Users that are interested in kactus2dev are comparing it to the libraries listed below
Sorting:
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- Python-based IP-XACT parser and utilities☆143Jun 13, 2024Updated last year
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆20May 12, 2025Updated 10 months ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Feb 23, 2026Updated 3 weeks ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 4 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,396Feb 13, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated 2 weeks ago
- Small footprint and configurable HyperBus core☆14Jul 6, 2022Updated 3 years ago
- An abstraction library for interfacing EDA tools☆754Mar 11, 2026Updated last week
- SystemC/TLM-2.0 Co-simulation framework☆273May 21, 2025Updated 10 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆320Jun 30, 2025Updated 8 months ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- Code generation tool for control and status registers☆450Mar 14, 2026Updated last week
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 9 months ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- cocotb: Python-based chip (RTL) verification☆2,284Mar 13, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- D3.js and ELK based schematic visualizer☆115Feb 27, 2024Updated 2 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆222Dec 23, 2025Updated 2 months ago
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- Digital Circuit rendering engine☆39Jul 30, 2025Updated 7 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- SystemRDL 2.0 language compiler front-end☆275Mar 8, 2026Updated 2 weeks ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- Hardware Description Languages☆1,127Jul 14, 2025Updated 8 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆300Feb 17, 2026Updated last month
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- FuseSoC standard core library☆157Mar 11, 2026Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆653Jan 19, 2026Updated 2 months ago
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆707Updated this week
- SystemVerilog compiler and language services☆985Updated this week
- Qbox☆84Mar 13, 2026Updated last week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆132Mar 14, 2026Updated last week
- Python library for parsing module definitions and instantiations from SystemVerilog files☆26Apr 29, 2021Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago