Alternatives and similar repositories for kactus2dev

Users that are interested in kactus2dev are comparing it to the libraries listed below

• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆311Updated 5 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆269Updated last month
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆220Updated this week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 6 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 10 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆207Updated last year
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆162Updated 3 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆352Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated 2 weeks ago
• svunit / svunit
  ☆207Updated 9 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆142Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated last month
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆308Updated 2 months ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 2 months ago
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last month
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆223Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆263Updated 7 months ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆134Updated 2 weeks ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆298Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆352Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆174Updated 4 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 3 weeks ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆125Updated 2 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 10 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago