Alternatives and similar repositories for kactus2dev

Users that are interested in kactus2dev are comparing it to the libraries listed below

• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆255Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆221Updated 3 weeks ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆213Updated 3 weeks ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆298Updated 2 weeks ago
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated 8 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆399Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 5 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆137Updated 3 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆333Updated this week
• kevinpt / symbolator
  HDL symbol generator
  ☆191Updated 2 years ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆277Updated 5 years ago
• svunit / svunit
  ☆204Updated 4 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆278Updated this week
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆133Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆161Updated last month
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆251Updated last month
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆216Updated 8 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆60Updated 5 months ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 4 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆284Updated 2 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆328Updated last week
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆137Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated 2 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆190Updated this week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago