Alternatives and similar repositories for kactus2dev

Users that are interested in kactus2dev are comparing it to the libraries listed below

• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 8 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆254Updated 3 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 4 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated 3 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆136Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆395Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆328Updated this week
• svunit / svunit
  ☆201Updated 3 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆298Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆113Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆327Updated this week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆248Updated last month
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆166Updated last month
• raysalemi / Python4RTLVerification
  ☆160Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆94Updated 3 weeks ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆147Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 7 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆282Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆178Updated 2 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆434Updated this week
• accellera-official / uvm-core
  ☆86Updated 9 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆187Updated last week
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆213Updated this week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆132Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆359Updated 3 weeks ago