Alternatives and similar repositories for sv-1800-2012

Users that are interested in sv-1800-2012 are comparing it to the libraries listed below

• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆58Updated last year
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated 2 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated 3 weeks ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 3 weeks ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆38Updated 2 months ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆135Updated last year
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆38Updated 6 years ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated last week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆115Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆141Updated 6 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 8 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated 2 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 6 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• wavedrom / vcd
  Value Change Dump (VCD) parser
  ☆36Updated 7 months ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆125Updated 3 months ago