Alternatives and similar repositories for sv-1800-2012

Users that are interested in sv-1800-2012 are comparing it to the libraries listed below

• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated this week
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆59Updated this week
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated 2 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 5 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆138Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆129Updated last month
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆70Updated this week
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 10 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆81Updated 3 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆39Updated 6 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 weeks ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆117Updated last month
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated this week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆167Updated 2 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆62Updated 2 years ago
• wavedrom / vcd
  Value Change Dump (VCD) parser
  ☆38Updated 10 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated 4 months ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆35Updated 10 years ago