Beautify SystemVerilog code in VSCode through Verible
☆23Apr 15, 2026Updated 2 months ago
Alternatives and similar repositories for systemverilog-formatter-vscode
Users that are interested in systemverilog-formatter-vscode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog support in VS Code☆153Jun 10, 2026Updated last week
- Render waveforms inside VSCode with WaveDrom☆40May 25, 2026Updated 3 weeks ago
- ☆12Nov 18, 2025Updated 7 months ago
- 它现在不仅有真值表，还有主范式、最简范式、王浩算法、手动等值演算 | 离散数学 Open Project☆17Sep 10, 2025Updated 9 months ago
- C++11 port of the Diff, Match and Patch libraries for Plain Text.☆12Mar 4, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Enumerate raw input devices and receive input events with device ID on Windows.☆12Sep 13, 2023Updated 2 years ago
- An extremely light weight tiny-YOLO inference engine targeted towards OpenCL hardware.☆16Oct 15, 2017Updated 8 years ago
- ☆11Jan 2, 2020Updated 6 years ago
- [deprecated]use mshr-h/vscode-verilog-hdl-support☆24Nov 3, 2018Updated 7 years ago
- Office implementation of "3D-Aware Hypothesis & Verification for Generalizable Relative Object Pose Estimation", ICLR 2024☆12Nov 5, 2024Updated last year
- Bazel build rules for GNU M4☆18Apr 6, 2026Updated 2 months ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- ☆15Mar 25, 2020Updated 6 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- ☆18Jan 21, 2025Updated last year
- Yet another dynamic batch sampler for variable sequence data in PyTorch.☆13Dec 9, 2021Updated 4 years ago
- SystemVerilog FSM generator☆39May 10, 2026Updated last month
- Test of parallel compression acceleration☆16Sep 8, 2024Updated last year
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 5 months ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- Magma Hackathon☆12Mar 4, 2020Updated 6 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Extended and external tests for Verilator testing☆18May 12, 2026Updated last month
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 2 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 11 years ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 8 years ago
- tmux plugin to show CPU temperature☆11Feb 25, 2022Updated 4 years ago
- [April 2025 0.7.0 (legacy support); June-2019, 2.2.4] A set of modifications to ctools and ld64 that enable support for older systems wit…☆28Apr 27, 2025Updated last year
- Convert tag files (ctags, gccxml, etc) to databases (sqlite, mysql, etc)☆13Mar 30, 2015Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ELF prelinking utility to speed up dynamic linking [unofficial mirror]☆11Jan 27, 2018Updated 8 years ago
- Fork of ag with added support for PCRE2 and ~/.agrc☆15Jan 30, 2022Updated 4 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 3 months ago
- Design contest for DAC 2018☆17Apr 12, 2018Updated 8 years ago
- Official repository for paper "UniDemoiré: Towards Universal Image Demoiréing with Data Generation and Synthesis"☆29Apr 9, 2025Updated last year
- A verilog parser☆19Apr 12, 2024Updated 2 years ago