Alternatives and similar repositories for systemverilog-formatter-vscode

Users that are interested in systemverilog-formatter-vscode are comparing it to the libraries listed below

• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆146Updated 11 months ago
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode using Ctags
  ☆37Updated 4 months ago
• accellera / uvm
  ☆60Updated 9 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated 2 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated last month
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆112Updated 2 years ago
• antoinemadec / uvm_code_gen
  Simple template-based UVM code generator
  ☆29Updated 3 years ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last month
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆118Updated 3 months ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆87Updated 4 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• accellera-official / uvm-core
  ☆109Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated last week
• svunit / svunit
  ☆208Updated 10 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆73Updated last week
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆36Updated 11 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆103Updated 3 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆35Updated 8 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆279Updated last month
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆203Updated 4 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 11 months ago
• mxg / svx
  SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity
  ☆33Updated last year
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year