Beautify SystemVerilog code in VSCode through Verible
☆22Jun 28, 2026Updated last month
Alternatives and similar repositories for systemverilog-formatter-vscode
Users that are interested in systemverilog-formatter-vscode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog support in VS Code☆154Updated this week
- Render waveforms inside VSCode with WaveDrom☆40May 25, 2026Updated 2 months ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- ☆13Nov 18, 2025Updated 8 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- verilog实现CLAHE(限制对比度自适应直方图均衡化)算法,并进行资源优化,含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆20Apr 30, 2026Updated 2 months ago
- 它现在不仅有真值表,还有主范式、最简范式、王浩算法、手动等值演算 | 离散数学 Open Project☆17Sep 10, 2025Updated 10 months ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆15Jun 25, 2025Updated last year
- Enumerate raw input devices and receive input events with device ID on Windows.☆14Sep 13, 2023Updated 2 years ago
- [deprecated]use mshr-h/vscode-verilog-hdl-support☆24Nov 3, 2018Updated 7 years ago
- Bazel build rules for GNU M4☆18Apr 6, 2026Updated 3 months ago
- ☆15Mar 25, 2020Updated 6 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- SystemVerilog FSM generator☆39May 10, 2026Updated 2 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- ☆17Jul 21, 2025Updated last year
- Yet another dynamic batch sampler for variable sequence data in PyTorch.☆13Dec 9, 2021Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆57Jan 5, 2026Updated 6 months ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- Magma Hackathon☆12Mar 4, 2020Updated 6 years ago
- A Python package for floating-point binary fractions. Do math in base 2!☆19Aug 3, 2022Updated 3 years ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Extended and external tests for Verilator testing☆19Jul 6, 2026Updated 3 weeks ago
- Open source implementation of a Verilog formatter☆185Jan 27, 2022Updated 4 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 weeks ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 11 years ago
- tmux plugin to show CPU temperature☆11Feb 25, 2022Updated 4 years ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- Design contest for DAC 2018☆17Apr 12, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Fortran language frontend for LLVM☆26Sep 7, 2013Updated 12 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- ☆22Mar 18, 2019Updated 7 years ago
- I2C models for cocotb☆46Mar 18, 2026Updated 4 months ago
- a repo for docker http pull image☆20Oct 31, 2024Updated last year
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- [ECCV 2024] Official PyTorch implementation of the paper "Scene-aware Human Motion Forecasting via Mutual Distance Prediction"☆15Nov 14, 2024Updated last year