mshr-h / vscode-verilog-hdl-supportLinks
HDL support for VS Code
☆344Updated last week
Alternatives and similar repositories for vscode-verilog-hdl-support
Users that are interested in vscode-verilog-hdl-support are comparing it to the libraries listed below
Sorting:
- SystemVerilog support in VS Code☆145Updated 10 months ago
- Verilog formatter☆199Updated last year
- Open source implementation of a Verilog formatter☆183Updated 3 years ago
- A git-friendly Vivado wrapper☆243Updated last year
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆678Updated last week
- lowRISC Style Guides☆472Updated last month
- Test suite designed to check compliance with the SystemVerilog standard.☆352Updated this week
- SystemVerilog to Verilog conversion☆686Updated last month
- Common SystemVerilog components☆689Updated this week
- SpinalHDL-tutorial based on Jupyter Notebook☆147Updated last year
- UVM 1.2 port to Python☆256Updated 10 months ago
- Code generation tool for control and status registers☆435Updated this week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆430Updated 3 months ago
- AXI interface modules for Cocotb☆302Updated 2 months ago
- Bus bridges and other odds and ends☆612Updated 8 months ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆310Updated 5 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆549Updated 2 months ago
- SystemRDL 2.0 language compiler front-end☆268Updated 3 weeks ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆458Updated last month
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆400Updated 3 months ago
- The UVM written in Python☆489Updated last week
- Xilinx Tcl Store☆369Updated 2 weeks ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆278Updated 5 years ago
- Code used in☆199Updated 8 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆627Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆287Updated this week
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆759Updated last year
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆144Updated last year
- ☆103Updated last year