mshr-h / vscode-verilog-hdl-supportView external linksLinks
HDL support for VS Code
☆352Feb 10, 2026Updated last week
Alternatives and similar repositories for vscode-verilog-hdl-support
Users that are interested in vscode-verilog-hdl-support are comparing it to the libraries listed below
Sorting:
- SystemVerilog support in VS Code☆148Feb 18, 2025Updated 11 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,769Dec 22, 2025Updated last month
- SystemVerilog language server☆560Updated this week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆691Dec 14, 2025Updated 2 months ago
- SystemVerilog compiler and language services☆948Updated this week
- A SystemVerilog Language Server☆194Nov 30, 2025Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week
- SystemVerilog/Verilog support for vscode using Ctags☆37Sep 19, 2025Updated 4 months ago
- SystemVerilog linter☆377Nov 6, 2025Updated 3 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆445Sep 6, 2025Updated 5 months ago
- Icarus Verilog☆3,324Feb 9, 2026Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 3 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,387Updated this week
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 2 years ago
- SystemVerilog to Verilog conversion☆701Nov 24, 2025Updated 2 months ago
- Open source implementation of a Verilog formatter☆182Jan 27, 2022Updated 4 years ago
- cocotb: Python-based chip (RTL) verification☆2,251Feb 10, 2026Updated last week
- Verilator open-source SystemVerilog simulator and lint system☆3,356Updated this week
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- ☆129Nov 17, 2025Updated 3 months ago
- An abstraction library for interfacing EDA tools☆750Feb 10, 2026Updated last week
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆904Feb 7, 2026Updated last week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆813Feb 10, 2026Updated last week
- Common SystemVerilog components☆708Feb 6, 2026Updated last week
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆315Jun 30, 2025Updated 7 months ago
- Unit testing for cocotb☆166Dec 6, 2025Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆645Jan 19, 2026Updated 3 weeks ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Oct 22, 2024Updated last year
- An Open-source FPGA IP Generator☆1,050Updated this week
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,492Feb 10, 2026Updated last week
- Code generation tool for control and status registers☆443Jan 7, 2026Updated last month
- 在vscode上的数字设计开发插件☆394Jan 27, 2023Updated 3 years ago
- An open-source static random access memory (SRAM) compiler.☆1,002Jan 16, 2026Updated last month
- Scala based HDL☆1,922Updated this week
- The UVM written in Python☆501Feb 10, 2026Updated last week