Alternatives and similar repositories for vscode-verilog-hdl-support

Users that are interested in vscode-verilog-hdl-support are comparing it to the libraries listed below

• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆139Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• ericsonj / verilog-format
  Verilog formatter
  ☆192Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆429Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆563Updated last month
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆262Updated last year
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆619Updated 2 months ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆438Updated 3 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆631Updated 2 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆349Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆467Updated 3 years ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆324Updated this week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆251Updated 2 months ago
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆179Updated 3 years ago
• dalance / svls
  SystemVerilog language server
  ☆508Updated last month
• rggen / rggen
  Code generation tool for control and status registers
  ☆391Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆500Updated 3 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆136Updated 11 months ago
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆358Updated 2 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆346Updated 2 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,287Updated last week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆616Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆333Updated last week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆251Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated last week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆170Updated 2 months ago