HDL support for VS Code
☆366May 1, 2026Updated last week
Alternatives and similar repositories for vscode-verilog-hdl-support
Users that are interested in vscode-verilog-hdl-support are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog support in VS Code☆153Feb 18, 2025Updated last year
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,834Mar 13, 2026Updated last month
- SystemVerilog/Verilog support for vscode using Ctags☆38Sep 19, 2025Updated 7 months ago
- SystemVerilog language server☆574Apr 2, 2026Updated last month
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆711Dec 14, 2025Updated 4 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog compiler and language services☆1,027Updated this week
- A SystemVerilog Language Server☆198Nov 30, 2025Updated 5 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆375Updated this week
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- Icarus Verilog☆3,434Updated this week
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆470Mar 30, 2026Updated last month
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆459Apr 5, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,413Feb 13, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verilator open-source SystemVerilog simulator and lint system☆3,587Updated this week
- SystemVerilog linter☆381Nov 6, 2025Updated 6 months ago
- cocotb: Python-based chip (RTL) verification☆2,366Updated this week
- HDL symbol generator☆202Feb 2, 2023Updated 3 years ago
- SystemVerilog to Verilog conversion☆725Mar 28, 2026Updated last month
- ☆133Nov 17, 2025Updated 5 months ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆964Apr 21, 2026Updated 2 weeks ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Oct 22, 2024Updated last year
- Unit testing for cocotb☆169Apr 18, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- VUnit is a unit testing framework for VHDL/SystemVerilog☆826Apr 22, 2026Updated 2 weeks ago
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year
- UVM 1.2 port to Python☆260Feb 9, 2025Updated last year
- Common SystemVerilog components☆743Updated this week
- An abstraction library for interfacing EDA tools☆765Apr 24, 2026Updated 2 weeks ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆324Jun 30, 2025Updated 10 months ago
- ☆12Nov 18, 2025Updated 5 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆660Apr 29, 2026Updated last week
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 在vscode上的数字设计开发插件☆394Jan 27, 2023Updated 3 years ago
- Code generation tool for control and status registers☆455Apr 19, 2026Updated 2 weeks ago
- The UVM written in Python☆537Apr 27, 2026Updated last week
- An Open-source FPGA IP Generator☆1,097Updated this week
- Parse FSDB waveform files☆22Apr 13, 2026Updated 3 weeks ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 4 years ago
- Waveform Viewer Extension for VScode☆334May 1, 2026Updated last week