Alternatives and similar repositories for YAC6xSim:

Users that are interested in YAC6xSim are comparing it to the libraries listed below

• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆25Updated 3 months ago
• shengwenliang / fpga-nvme-controller
  Chisel NVMe controller
  ☆15Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆47Updated 2 years ago
• himanshu5-prog / vortexGPU
  ☆19Updated 3 years ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• zenonxiu81 / arm_system_register_parser
  A python parser for decoding arm aarch32 and aarch64 system registers
  ☆15Updated last year
• edgarigl / tlmu
  TLMu - Transaction Level eMulator
  ☆33Updated 10 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆31Updated 5 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆18Updated 10 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆41Updated 7 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 2 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆72Updated 5 months ago
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆19Updated 10 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 6 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆23Updated 4 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆46Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆16Updated 11 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last week
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆33Updated last year
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆33Updated 6 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆45Updated last week
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆21Updated 8 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆14Updated this week
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆24Updated 6 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆30Updated last month