ericsonj / verilog-formatView external linksLinks
Verilog formatter
☆198Jan 2, 2024Updated 2 years ago
Alternatives and similar repositories for verilog-format
Users that are interested in verilog-format are comparing it to the libraries listed below
Sorting:
- Open source implementation of a Verilog formatter☆182Jan 27, 2022Updated 4 years ago
- ☆11Nov 18, 2025Updated 2 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,769Dec 22, 2025Updated last month
- SystemVerilog language server☆560Updated this week
- Open source implementation of a Verilog formatter☆23Jun 18, 2020Updated 5 years ago
- SystemVerilog linter☆377Nov 6, 2025Updated 3 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs (DAC'23)☆11Apr 13, 2023Updated 2 years ago
- ☆10Jul 23, 2023Updated 2 years ago
- ☆129Nov 17, 2025Updated 2 months ago
- HDL support for VS Code☆352Updated this week
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 8 months ago
- ☆12Jul 20, 2022Updated 3 years ago
- ☆17Jun 5, 2024Updated last year
- Verilog network module. Models network traffic from pcap to AXI-Stream☆23Apr 24, 2021Updated 4 years ago
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- RISC-V SingleCycle/Pipeline CPU (lab of ZJU Computer System Series)☆14Jul 6, 2023Updated 2 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆463Nov 4, 2025Updated 3 months ago
- A SapientML plugin of SapientMLGenerator☆11Dec 23, 2025Updated last month
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 6 years ago
- SystemVerilog to Verilog conversion☆701Nov 24, 2025Updated 2 months ago
- SystemVerilog compiler and language services☆948Updated this week
- New implementation of xeCJK☆22Feb 1, 2023Updated 3 years ago
- A SystemVerilog Language Server☆193Nov 30, 2025Updated 2 months ago
- cocotb: Python-based chip (RTL) verification☆2,251Updated this week
- Verilog AXI components for FPGA implementation☆1,952Feb 27, 2025Updated 11 months ago
- Benchmarking PyTorch 2.0 different models☆20Mar 19, 2023Updated 2 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Dec 8, 2017Updated 8 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 2 years ago
- synthesiseable ieee 754 floating point library in verilog☆717Mar 13, 2023Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- My personal competitive programming repository.☆10Apr 12, 2020Updated 5 years ago
- Digital timing diagram rendering engine☆3,345Jul 10, 2025Updated 7 months ago
- Various HDL (Verilog) IP Cores☆873Jul 1, 2021Updated 4 years ago
- ☆29Feb 20, 2024Updated last year
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- RISC-V kernel step-by-step implmenetation☆12Nov 12, 2019Updated 6 years ago