Verilog formatter
☆208Mar 25, 2026Updated 7 months ago
Alternatives and similar repositories for verilog-format
Users that are interested in verilog-format are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open source implementation of a Verilog formatter☆187Jan 27, 2022Updated 4 years ago
- ☆13Oct 16, 2026Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,974Updated this week
- VSCode extension for enhancing verilog☆25Apr 27, 2024Updated 2 years ago
- SystemVerilog language server☆587Oct 14, 2026Updated 2 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog linter☆394Nov 6, 2025Updated 11 months ago
- Verilog/SystemVerilog support for VS Code☆388Updated this week
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- ☆25Jul 14, 2025Updated last year
- ☆12Jul 20, 2022Updated 4 years ago
- ☆136Nov 17, 2025Updated 11 months ago
- RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs (DAC'23)☆11Apr 13, 2023Updated 3 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆483Jun 10, 2026Updated 4 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- SystemVerilog to Verilog conversion☆758Aug 18, 2026Updated 2 months ago
- Verilog AXI components for FPGA implementation☆2,167Feb 27, 2025Updated last year
- Icarus Verilog☆3,705Updated this week
- Digital timing diagram rendering engine☆3,513Updated this week
- A SystemVerilog Language Server☆211Nov 30, 2025Updated 11 months ago
- SystemVerilog compiler and language services☆1,173Updated this week
- A Preprocessor for Verilog HDL written in C++☆11May 26, 2012Updated 14 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆743Oct 11, 2026Updated 2 weeks ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 7 months ago
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- ☆13Oct 23, 2022Updated 4 years ago
- HDL symbol generator☆206Feb 2, 2023Updated 3 years ago
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 7 years ago
- DVSim is a build and run system written in Python that runs a variety of EDA tool flows☆16Oct 24, 2026Updated last week
- ☆10Nov 12, 2019Updated 6 years ago
- cocotb: Python-based chip (RTL) verification☆2,558Updated this week
- Verilog/SystemVerilog Syntax and Omni-completion☆425Aug 3, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Implementation of different types of adder circuits☆16Jan 5, 2016Updated 10 years ago
- 使用 VSCode 舒适地开发 Verilog☆36Aug 11, 2020Updated 6 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,739Updated this week
- HDL Obfuscator☆13May 13, 2021Updated 5 years ago
- Getting started running RISC-V Linux☆18Apr 15, 2021Updated 5 years ago
- Yosys Open SYnthesis Suite☆4,855Updated this week