Verilog formatter
☆200Mar 25, 2026Updated this week
Alternatives and similar repositories for verilog-format
Users that are interested in verilog-format are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open source implementation of a Verilog formatter☆181Jan 27, 2022Updated 4 years ago
- ☆12Nov 18, 2025Updated 4 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,797Mar 13, 2026Updated 2 weeks ago
- VSCode extension for enhancing verilog☆25Apr 27, 2024Updated last year
- SystemVerilog linter☆379Nov 6, 2025Updated 4 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SystemVerilog language server☆567Mar 18, 2026Updated last week
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- HDL support for VS Code☆358Mar 20, 2026Updated last week
- ☆12Jul 20, 2022Updated 3 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- ☆132Nov 17, 2025Updated 4 months ago
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs (DAC'23)☆11Apr 13, 2023Updated 2 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆468Nov 4, 2025Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- ☆24Jul 14, 2025Updated 8 months ago
- SystemVerilog compiler and language services☆989Mar 22, 2026Updated last week
- Yet another implementation of TI C6x DSP simulator☆12Jan 16, 2014Updated 12 years ago
- Verilog AXI components for FPGA implementation☆1,996Feb 27, 2025Updated last year
- Digital timing diagram rendering engine☆3,368Jul 10, 2025Updated 8 months ago
- git clone of http://code.google.com/p/axi-bfm/☆19May 21, 2013Updated 12 years ago
- A SapientML plugin of SapientMLGenerator☆11Updated this week
- SystemVerilog to Verilog conversion☆710Nov 24, 2025Updated 4 months ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Verdi like, verilog code signal trace and show hierarchy script☆19Oct 16, 2019Updated 6 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 4 years ago
- A SystemVerilog Language Server☆195Nov 30, 2025Updated 3 months ago
- cocotb: Python-based chip (RTL) verification☆2,289Mar 19, 2026Updated last week
- HDL Obfuscator☆12May 13, 2021Updated 4 years ago
- 使用 VSCode 舒适地开发 Verilog☆37Aug 11, 2020Updated 5 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,528Mar 18, 2026Updated last week
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- A C version of Branch Predictor Simulator☆17Jul 10, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆10Nov 12, 2019Updated 6 years ago
- AI-ML-NLP Task Group☆13Aug 10, 2023Updated 2 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆703Dec 14, 2025Updated 3 months ago
- Benchmarking PyTorch 2.0 different models☆20Mar 19, 2023Updated 3 years ago
- Getting started running RISC-V Linux☆18Apr 15, 2021Updated 4 years ago
- Icarus Verilog☆3,389Mar 21, 2026Updated last week
- Repository for AI model benchmarking on TT-Buda☆16Feb 9, 2026Updated last month