Minres / RDL-EditorLinks
A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
☆12Updated last year
Alternatives and similar repositories for RDL-Editor
Users that are interested in RDL-Editor are comparing it to the libraries listed below
Sorting:
- Import and export IP-XACT XML register models☆36Updated last month
- SystemVerilog Linter based on pyslang☆31Updated 7 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated last year
- Common SystemVerilog RTL modules for RgGen☆15Updated last week
- SystemVerilog Logger☆19Updated 3 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆59Updated last month
- Generate UVM register model from compiled SystemRDL input☆60Updated last month
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆64Updated 3 weeks ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆73Updated 2 weeks ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 4 months ago
- Running Python code in SystemVerilog☆71Updated 6 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆48Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- ☆26Updated 2 years ago
- A CSV file parser, written in SystemVerilog☆26Updated 9 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆25Updated 4 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆14Updated last week
- Python interface for cross-calling with HDL☆45Updated this week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago