google / verilogppLinks
☆17Updated last year
Alternatives and similar repositories for verilogpp
Users that are interested in verilogpp are comparing it to the libraries listed below
Sorting:
- SRAM build space for SKY130 provided by SkyWater.☆22Updated 3 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆17Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆48Updated 2 years ago
- Extended and external tests for Verilator testing☆16Updated 2 weeks ago
- SRAM build space for the GF180MCU provided by GlobalFoundries.☆10Updated 2 years ago
- Primitives for SKY130 provided by SkyWater.☆26Updated last year
- Advanced Debug Interface☆15Updated 4 months ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆17Updated 2 years ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆13Updated 4 years ago
- "High density" digital standard cells for SKY130 provided by SkyWater.☆16Updated 2 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆26Updated 2 years ago
- AXI X-Bar☆19Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 10 months ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 10 months ago
- SKY130 ReRAM and examples (SkyWater Provided)☆38Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆35Updated last week
- SystemVerilog Logger☆17Updated 2 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆34Updated 7 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- few python scripts to clone all IP cores from opencores.org☆22Updated last year
- ☆16Updated 7 months ago
- Hardware and script files related to dynamic partial reconfiguration☆9Updated 7 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆19Updated 10 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago