google / verilogppLinks
☆17Updated last year
Alternatives and similar repositories for verilogpp
Users that are interested in verilogpp are comparing it to the libraries listed below
Sorting:
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- SRAM build space for SKY130 provided by SkyWater.☆24Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- Advanced Debug Interface☆14Updated 11 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 7 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆32Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Updated last year
- ☆33Updated last month
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- ☆33Updated 3 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- AXI X-Bar☆19Updated 5 years ago
- Import and export IP-XACT XML register models☆36Updated 2 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Updated 3 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- ☆15Updated 2 weeks ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- SystemVerilog Logger☆19Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Open Source PHY v2☆32Updated last year
- APB Logic☆22Updated 2 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆33Updated last month
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- ☆22Updated 6 years ago