google / verilogppLinks
☆17Updated last year
Alternatives and similar repositories for verilogpp
Users that are interested in verilogpp are comparing it to the libraries listed below
Sorting:
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- SRAM build space for SKY130 provided by SkyWater.☆24Updated 4 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- Advanced Debug Interface☆14Updated 10 months ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆20Updated 4 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- Open Source PHY v2☆31Updated last year
- SystemVerilog Logger☆19Updated 2 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆50Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated last week
- ☆22Updated 6 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 2 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆32Updated 7 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- ☆14Updated 2 months ago
- APB Logic☆22Updated last month
- Import and export IP-XACT XML register models☆36Updated last month
- ☆32Updated 3 weeks ago
- ☆21Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆23Updated last year
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated last year