Alternatives and similar repositories for scr1-sdk:

Users that are interested in scr1-sdk are comparing it to the libraries listed below

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• syntacore / sc-bl
  Syntacore first stage bootloader
  ☆10Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆119Updated 5 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆122Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆81Updated 2 weeks ago
• freecores / i2c
  I2C controller core
  ☆39Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 5 years ago
• syntacore / fpga-sdk-prj
  FPGA-based SDK projects for SCRx cores
  ☆18Updated 3 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆35Updated 2 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆120Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆115Updated this week
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆87Updated 10 months ago
• jamieiles / uart
  Verilog UART
  ☆148Updated 11 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆113Updated 6 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆86Updated last month
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆61Updated 2 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆117Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 2 years ago