Alternatives and similar repositories for scr1-sdk

Users that are interested in scr1-sdk are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆124Updated 6 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 8 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆124Updated 4 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆141Updated 6 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆97Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• open-design / riscv-soc-cores
  ☆38Updated 4 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 6 months ago
• Digilent / digilent-vivado-scripts
  ☆69Updated last month
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆102Updated 6 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆97Updated 11 months ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated last week
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆156Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆184Updated 8 months ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆174Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆118Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated 2 months ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆113Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated 3 months ago