Alternatives and similar repositories for scr1-sdk:

Users that are interested in scr1-sdk are comparing it to the libraries listed below

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆109Updated 5 years ago
• syntacore / sc-bl
  Syntacore first stage bootloader
  ☆9Updated 3 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆82Updated 3 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆75Updated 3 weeks ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆108Updated 6 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆63Updated 2 weeks ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆69Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆125Updated this week
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆125Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆86Updated 4 months ago
• jamieiles / uart
  Verilog UART
  ☆133Updated 11 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆61Updated 2 years ago
• sifive / elf2hex
  Converts ELF files to HEX files that are suitable for Verilog's readmemh.
  ☆83Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆152Updated 9 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆84Updated 4 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆117Updated 4 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆148Updated 6 years ago
• syntacore / fpga-sdk-prj
  FPGA-based SDK projects for SCRx cores
  ☆17Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆65Updated 9 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆170Updated last month
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆51Updated 5 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆99Updated 6 years ago