syntacore / scr1-sdk

Related projects ⓘ

Alternatives and complementary repositories for scr1-sdk

• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆67Updated 4 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆102Updated 6 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆114Updated 4 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• sifive / elf2hex
  Converts ELF files to HEX files that are suitable for Verilog's readmemh.
  ☆81Updated 2 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆60Updated 3 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago
• syntacore / fpga-sdk-prj
  FPGA-based SDK projects for SCRx cores
  ☆17Updated 2 years ago
• jamieiles / uart
  Verilog UART
  ☆121Updated 11 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆73Updated 10 months ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆48Updated 8 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆85Updated 2 months ago
• chipsalliance / Cores-SweRV_fpga
  ☆39Updated 4 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆89Updated 3 years ago
• syntacore / sc-bl
  Syntacore first stage bootloader
  ☆9Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆123Updated 5 years ago
• Digilent / digilent-vivado-scripts
  ☆63Updated 4 months ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆55Updated 2 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆101Updated 3 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆85Updated 3 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆139Updated 4 months ago