skordal / potatoLinks
A simple RISC-V processor for use in FPGA designs.
☆279Updated last year
Alternatives and similar repositories for potato
Users that are interested in potato are comparing it to the libraries listed below
Sorting:
- A simple, basic, formally verified UART controller☆311Updated last year
- Small footprint and configurable DRAM core☆444Updated last week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆275Updated 5 years ago
- RISC-V CPU Core☆389Updated 4 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆672Updated 3 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆328Updated 10 months ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆410Updated last month
- Verilog implementation of a RISC-V core☆125Updated 7 years ago
- Basic RISC-V CPU implementation in VHDL.☆169Updated 5 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆447Updated last year
- Bus bridges and other odds and ends☆593Updated 6 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆326Updated 3 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated last week
- CORE-V Family of RISC-V Cores☆302Updated 8 months ago
- ☆245Updated 2 years ago
- A 32-bit RISC-V soft processor☆315Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆274Updated last week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 7 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆444Updated 5 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆409Updated 3 weeks ago
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆155Updated 7 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆556Updated 2 months ago
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆527Updated 2 years ago
- VeeR EL2 Core☆299Updated 2 weeks ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆311Updated 2 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆282Updated 5 years ago
- A simple RISC V core for teaching☆197Updated 3 years ago