skordal / potatoLinks
A simple RISC-V processor for use in FPGA designs.
☆282Updated last year
Alternatives and similar repositories for potato
Users that are interested in potato are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable DRAM core☆459Updated this week
- A simple, basic, formally verified UART controller☆316Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- RISC-V CPU Core☆394Updated 5 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- Bus bridges and other odds and ends☆609Updated 7 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆676Updated 4 months ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆297Updated this week
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆454Updated last year
- Verilog implementation of a RISC-V core☆131Updated 7 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆283Updated last week
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆412Updated 3 weeks ago
- Example designs showing different ways to use F4PGA toolchains.☆278Updated last year
- Basic RISC-V CPU implementation in VHDL.☆171Updated 5 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆328Updated 3 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆566Updated 3 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆447Updated 6 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆158Updated 7 years ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆414Updated this week
- VeeR EL2 Core☆305Updated 2 weeks ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆599Updated 4 months ago
- ☆250Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆157Updated 8 months ago
- CORE-V Family of RISC-V Cores☆308Updated 9 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- Linux on LiteX-VexRiscv☆666Updated 2 months ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆374Updated 2 years ago
- A Video display simulator☆174Updated 6 months ago
- VHDL synthesis (based on ghdl)☆353Updated last month