skordal / potatoLinks
A simple RISC-V processor for use in FPGA designs.
☆283Updated last year
Alternatives and similar repositories for potato
Users that are interested in potato are comparing it to the libraries listed below
Sorting:
- A simple, basic, formally verified UART controller☆321Updated last year
- Small footprint and configurable DRAM core☆462Updated last week
- RISC-V CPU Core☆404Updated 7 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆283Updated 5 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆680Updated 6 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆334Updated last year
- Basic RISC-V CPU implementation in VHDL.☆172Updated 5 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆461Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆301Updated this week
- A 32-bit RISC-V soft processor☆320Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆452Updated 8 months ago
- Verilog implementation of a RISC-V core☆134Updated 7 years ago
- Bus bridges and other odds and ends☆629Updated 9 months ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆421Updated last month
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆600Updated 5 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆290Updated last month
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆415Updated last week
- CORE-V Family of RISC-V Cores☆318Updated 11 months ago
- Example designs showing different ways to use F4PGA toolchains.☆282Updated last year
- mor1kx - an OpenRISC 1000 processor IP core☆571Updated 5 months ago
- Linux on LiteX-VexRiscv☆678Updated 3 weeks ago
- ☆258Updated 3 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆125Updated 5 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆330Updated 4 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313Updated 2 years ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Updated 7 years ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆285Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Updated 10 months ago
- VeeR EL2 Core☆315Updated 3 weeks ago
- VHDL synthesis (based on ghdl)☆353Updated 2 weeks ago