skordal / potato
A simple RISC-V processor for use in FPGA designs.
☆266Updated 5 months ago
Alternatives and similar repositories for potato:
Users that are interested in potato are comparing it to the libraries listed below
- RISC-V CPU Core☆304Updated 7 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆637Updated 2 months ago
- Bus bridges and other odds and ends☆511Updated last week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆384Updated last week
- SystemVerilog to Verilog conversion☆585Updated last month
- VHDL synthesis (based on ghdl)☆317Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆399Updated last week
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆315Updated 3 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated last month
- A simple, basic, formally verified UART controller☆287Updated last year
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- Common SystemVerilog components☆560Updated 2 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆278Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆152Updated 9 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆148Updated 6 years ago
- Small footprint and configurable DRAM core☆388Updated 3 weeks ago
- FOSS Flow For FPGA☆368Updated 3 weeks ago
- ☆222Updated 2 years ago
- CORE-V Family of RISC-V Cores☆221Updated this week
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆563Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆451Updated 3 months ago
- VeeR EL2 Core☆259Updated this week
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 10 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆238Updated 2 months ago
- A huge VHDL library for FPGA development☆368Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆233Updated 3 weeks ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆274Updated 5 years ago
- Basic RISC-V CPU implementation in VHDL.☆165Updated 4 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆414Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 2 months ago