skordal / potato
A simple RISC-V processor for use in FPGA designs.
☆263Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for potato
- RISC-V CPU Core☆288Updated 5 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated this week
- A simple, basic, formally verified UART controller☆282Updated 9 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆259Updated 4 years ago
- Common SystemVerilog components☆518Updated this week
- Bus bridges and other odds and ends☆490Updated 10 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆291Updated 2 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆390Updated 3 weeks ago
- Small footprint and configurable DRAM core☆382Updated last month
- Basic RISC-V CPU implementation in VHDL.☆161Updated 4 years ago
- ☆215Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆438Updated 3 weeks ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆404Updated last week
- A 32-bit Microcontroller featuring a RISC-V core☆148Updated 6 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆310Updated 2 years ago
- VeeR EL2 Core☆251Updated this week
- CORE-V Family of RISC-V Cores☆208Updated 9 months ago
- SoC based on VexRiscv and ICE40 UP5K☆151Updated 7 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆225Updated last week
- Verilog implementation of a RISC-V core☆102Updated 6 years ago
- Example designs showing different ways to use F4PGA toolchains.☆267Updated 7 months ago
- mor1kx - an OpenRISC 1000 processor IP core☆497Updated last month
- SystemVerilog to Verilog conversion☆564Updated 3 weeks ago
- A simple RISC V core for teaching☆173Updated 2 years ago
- Linux on LiteX-VexRiscv☆588Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆216Updated 2 weeks ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆301Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆526Updated this week
- RISC-V Formal Verification Framework☆585Updated 2 years ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆551Updated 3 years ago