Alternatives and similar repositories for neorv32-verilog

Users that are interested in neorv32-verilog are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated 2 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆109Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆82Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆68Updated last month
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆112Updated 2 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆105Updated last year
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 10 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆48Updated last year
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆137Updated 3 weeks ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆128Updated last month
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆48Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆69Updated 8 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆140Updated 6 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 7 months ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆154Updated 3 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆124Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆77Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 6 months ago
• ldoolitt / vhd2vl
  ☆136Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆175Updated last week
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆90Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆102Updated 3 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆88Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆108Updated 4 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 5 months ago