stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
☆75Updated last week
Alternatives and similar repositories for neorv32-verilog:
Users that are interested in neorv32-verilog are comparing it to the libraries listed below
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆83Updated last year
- RISC-V Nox core☆62Updated 7 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆37Updated this week
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆70Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated 3 weeks ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆44Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆61Updated this week
- FuseSoC standard core library☆128Updated last month
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 10 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- Naive Educational RISC V processor☆79Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated last month
- Spen's Official OpenOCD Mirror☆48Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 4 months ago
- RISC-V 32-bit microcontroller developed in Verilog☆168Updated 3 weeks ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Verilog implementation of a RISC-V core☆109Updated 6 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 4 months ago
- RISC-V Verification Interface☆85Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆53Updated this week
- Mathematical Functions in Verilog☆90Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆89Updated 6 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆61Updated 4 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago