stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
☆73Updated this week
Alternatives and similar repositories for neorv32-verilog:
Users that are interested in neorv32-verilog are comparing it to the libraries listed below
- RISC-V Nox core☆62Updated 6 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆33Updated last week
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆58Updated 2 months ago
- FuseSoC standard core library☆125Updated 2 weeks ago
- Naive Educational RISC V processor☆78Updated 4 months ago
- Generic Register Interface (contains various adapters)☆106Updated 4 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆79Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- Spen's Official OpenOCD Mirror☆48Updated 11 months ago
- 64-bit multicore Linux-capable RISC-V processor☆84Updated 5 months ago
- SpinalHDL Hardware Math Library☆83Updated 7 months ago
- ☆59Updated 3 years ago
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated last month
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆142Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆49Updated this week
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆58Updated 3 months ago
- Open source ISS and logic RISC-V 32 bit project☆42Updated 2 months ago
- Simple 8-bit UART realization on Verilog HDL.☆96Updated 9 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- The multi-core cluster of a PULP system.☆69Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆87Updated 5 months ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- RISC-V Ibex core with Wishbone B4 interface☆14Updated 5 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆93Updated 3 years ago