stnolting / neorv32-setupsView external linksLinks
π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
β88Updated this week
Alternatives and similar repositories for neorv32-setups
Users that are interested in neorv32-setups are comparing it to the libraries listed below
Sorting:
- β»οΈ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.β101Dec 3, 2025Updated 2 months ago
- π₯οΈ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independeβ¦β1,977Feb 9, 2026Updated last week
- Virtual development board for HDL designβ42Mar 31, 2023Updated 2 years ago
- A first approach of getting a pure Ada program running on an FPGA with SaxonSOCβ11Apr 12, 2021Updated 4 years ago
- πΎ FreeRTOS port for the NEORV32 RISC-V Processor.β12Updated this week
- ulx3s ghdl examplesβ15Mar 6, 2021Updated 4 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industryβ12Jul 6, 2023Updated 2 years ago
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.β16Apr 10, 2025Updated 10 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boardsβ47Updated this week
- a project to check the FOSS synthesizers against vendors EDA toolsβ12Sep 26, 2020Updated 5 years ago
- VHDL related news.β27Updated this week
- VHDLproc is a VHDL preprocessorβ24May 12, 2022Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architectureβ51Jun 5, 2022Updated 3 years ago
- A VHDL Core Library.β18Mar 29, 2017Updated 8 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40Pβ155Oct 31, 2024Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 featuresβ32Jan 30, 2025Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDLβ51Updated this week
- general-coresβ21Jul 16, 2025Updated 7 months ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.β13Sep 22, 2025Updated 4 months ago
- π Add capacitive touch buttons to any FPGA!β102Mar 4, 2022Updated 3 years ago
- Interface definitions for VHDL-2019.β34Jan 12, 2026Updated last month
- Building and deploying container images for open source electronic design automation (EDA)β120Oct 3, 2024Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2β335Dec 11, 2024Updated last year
- cryptography ip-cores in vhdl / verilogβ41Feb 20, 2021Updated 4 years ago
- βοΈ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.β39Updated this week
- A usable language reference for VHDL that is concise, direct, and easy to understand.β26Sep 16, 2025Updated 5 months ago
- ECP5 FPGA DEV BOARDβ10Apr 19, 2021Updated 4 years ago
- Extracts specified data from a VCD file into CSV formβ10Jan 10, 2020Updated 6 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systemsβ12Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40Pβ258Nov 6, 2024Updated last year
- A huge VHDL library for FPGA and digital ASIC developmentβ449Feb 9, 2026Updated last week
- GSI Timing Gateware and Toolsβ14Updated this week
- Experiments with Cologne Chip's GateMate FPGA architectureβ17Nov 16, 2023Updated 2 years ago
- Standard and Curated cores, tested and working.β11Dec 29, 2022Updated 3 years ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.β10Jul 22, 2020Updated 5 years ago
- 32-bit RISC-V microcontrollerβ12Sep 11, 2021Updated 4 years ago
- vhdl related contentsβ11Apr 27, 2020Updated 5 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workβ¦β10Jan 13, 2022Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.β196Dec 11, 2025Updated 2 months ago