π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
β101Oct 12, 2026Updated last week
Alternatives and similar repositories for neorv32-setups
Users that are interested in neorv32-setups are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- β»οΈ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.β101Dec 3, 2025Updated 10 months ago
- π₯οΈ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independeβ¦β2,299Updated this week
- Specification of the Wishbone SoC Interconnect Architectureβ54Jun 5, 2022Updated 4 years ago
- Rust support for the open-source NEORV32 RISC-V microcontroller.β14Feb 19, 2026Updated 8 months ago
- Virtual development board for HDL designβ44Mar 31, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer β’ AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- πΎ FreeRTOS port for the NEORV32 RISC-V Processor.β16Updated this week
- Interface definitions for VHDL-2019.β36May 13, 2026Updated 5 months ago
- VHDLproc is a VHDL preprocessorβ25May 12, 2022Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards