VHDL compiler and simulator
☆851Jun 30, 2026Updated this week
Alternatives and similar repositories for nvc
Users that are interested in nvc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VHDL 2008/93/87 simulator☆2,840Updated this week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆835May 14, 2026Updated last month
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆261Jun 6, 2026Updated 3 weeks ago
- Style guide enforcement for VHDL☆245Jun 19, 2026Updated 2 weeks ago
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆451Apr 22, 2026Updated 2 months ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- A VHDL frontend for Yosys☆104Feb 27, 2017Updated 9 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- VHDL synthesis (based on ghdl)☆367Jun 22, 2026Updated last week
- A JSON library implemented in VHDL.☆85Feb 8, 2026Updated 4 months ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆606Jul 30, 2025Updated 11 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆68Jun 11, 2026Updated 3 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆467Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Flexible VHDL library☆197Jun 28, 2023Updated 3 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆69Feb 16, 2026Updated 4 months ago
- VHDL Language Support for VSCode☆73Mar 28, 2025Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Updated this week
- Yosys Open SYnthesis Suite☆4,553Jun 27, 2026Updated last week
- VHDL related news.☆27Updated this week
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆689Jul 16, 2025Updated 11 months ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- An open-source HDL register code generator fast enough to run in real time.☆89Updated this week
- cocotb: Python-based chip (RTL) verification☆2,422Jun 24, 2026Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆329Jun 30, 2025Updated last year
- 🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…☆2,154Jun 16, 2026Updated 2 weeks ago
- An abstract language model of VHDL written in Python.☆64Jun 25, 2026Updated last week
- Playing around with Formal Verification of Verilog and VHDL☆65Feb 22, 2021Updated 5 years ago
- Repurposing existing HDL tools to help writing better code☆224Jun 21, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆259Jun 26, 2026Updated last week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆79Jun 21, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- draws an SVG schematic from a JSON netlist☆800Jan 25, 2024Updated 2 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,429Updated this week
- Open Logic FPGA Standard Library☆973Jun 23, 2026Updated last week
- An abstraction library for interfacing EDA tools☆774Updated this week
- Yet Another VHDL tool☆30May 15, 2017Updated 9 years ago
- Language server based on ghdl☆103Jun 3, 2026Updated last month