nickg / nvcLinks
VHDL compiler and simulator
☆696Updated this week
Alternatives and similar repositories for nvc
Users that are interested in nvc are comparing it to the libraries listed below
Sorting:
- VUnit is a unit testing framework for VHDL/SystemVerilog☆775Updated 3 weeks ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆579Updated 4 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,293Updated this week
- nextpnr portable FPGA place and route tool☆1,444Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆243Updated 3 weeks ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)☆1,063Updated 2 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 6 months ago
- VHDL synthesis (based on ghdl)☆335Updated last week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆399Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆630Updated 2 weeks ago
- Documenting the Xilinx 7-series bit-stream format.☆801Updated 2 weeks ago
- cocotb: Python-based chip (RTL) verification☆1,986Updated this week
- An abstraction library for interfacing EDA tools☆690Updated 3 weeks ago
- Multi-platform nightly builds of open source digital design and verification tools☆1,059Updated this week
- ☆402Updated 2 weeks ago
- SERV - The SErial RISC-V CPU☆1,589Updated 2 weeks ago
- Place and route tool for FPGAs☆420Updated 5 years ago
- A Python toolbox for building complex digital hardware☆1,275Updated 3 weeks ago
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆455Updated 2 weeks ago
- Documenting the Lattice ECP5 bit-stream format.☆415Updated last month
- A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …☆653Updated this week
- A simple RISC-V processor for use in FPGA designs.☆274Updated 9 months ago
- Verilog library for ASIC and FPGA designers☆1,293Updated last year
- A small, light weight, RISC CPU soft core☆1,409Updated 3 months ago
- Hardware Description Languages☆1,036Updated 3 months ago
- A huge VHDL library for FPGA and digital ASIC development☆384Updated this week
- RISC-V Formal Verification Framework☆602Updated 3 years ago
- GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …☆782Updated 3 weeks ago
- FOSS Flow For FPGA☆388Updated 4 months ago
- Linux on LiteX-VexRiscv☆636Updated 3 weeks ago