Alternatives and similar repositories for nvc

Users that are interested in nvc are comparing it to the libraries listed below

• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆792Updated 2 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,344Updated 2 weeks ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,532Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆830Updated 4 months ago
• ghdl / ghdl-yosys-plugin
  VHDL synthesis (based on ghdl)
  ☆347Updated 2 weeks ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆596Updated 2 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆409Updated 3 weeks ago
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,308Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 3 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆475Updated 2 weeks ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆250Updated 3 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆716Updated last week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆679Updated last week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,099Updated last month
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆670Updated 4 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆428Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,468Updated 2 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆409Updated 9 months ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆853Updated 4 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,204Updated this week
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆611Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆279Updated last year
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆556Updated 2 months ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,070Updated 3 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,150Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,659Updated last week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,117Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆867Updated this week
• YosysHQ / arachne-pnr
  Place and route tool for FPGAs
  ☆422Updated 6 years ago