slaclab / surf
A huge VHDL library for FPGA development
☆372Updated this week
Alternatives and similar repositories for surf:
Users that are interested in surf are comparing it to the libraries listed below
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆385Updated this week
- Flexible VHDL library☆183Updated last year
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆235Updated last week
- Bus bridges and other odds and ends☆520Updated 2 weeks ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆568Updated 4 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated this week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆152Updated this week
- An abstraction library for interfacing EDA tools☆663Updated last week
- Common SystemVerilog components☆572Updated 2 weeks ago
- Style guide enforcement for VHDL☆198Updated 3 weeks ago
- A simple, basic, formally verified UART controller☆288Updated last year
- Open Logic FPGA Standard Library☆479Updated this week
- AXI interface modules for Cocotb☆233Updated last year
- Test suite designed to check compliance with the SystemVerilog standard.☆306Updated this week
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆515Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 10 months ago
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆381Updated 2 months ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆196Updated 3 months ago
- Code generation tool for control and status registers☆363Updated this week
- SystemVerilog to Verilog conversion☆590Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆312Updated last week
- lowRISC Style Guides☆388Updated 5 months ago
- Opensource DDR3 Controller☆265Updated this week
- Various HDL (Verilog) IP Cores☆743Updated 3 years ago
- The UVM written in Python☆401Updated last month
- A simple RISC-V processor for use in FPGA designs.☆267Updated 6 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆209Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆455Updated last week
- A DDR3 memory controller in Verilog for various FPGAs☆408Updated 3 years ago