slaclab / surfLinks
A huge VHDL library for FPGA and digital ASIC development
☆390Updated this week
Alternatives and similar repositories for surf
Users that are interested in surf are comparing it to the libraries listed below
Sorting:
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆399Updated last month
- Bus bridges and other odds and ends☆568Updated 2 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆171Updated this week
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆242Updated last week
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆580Updated 4 years ago
- Flexible VHDL library☆187Updated last year
- Common SystemVerilog components☆627Updated last week
- AXI interface modules for Cocotb☆267Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆264Updated this week
- Style guide enforcement for VHDL☆211Updated 2 months ago
- An abstraction library for interfacing EDA tools☆696Updated last week
- Opensource DDR3 Controller☆347Updated last week
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆625Updated 2 months ago
- The UVM written in Python☆434Updated 2 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆435Updated 9 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆352Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆290Updated 2 weeks ago
- Verilog UART☆490Updated 3 months ago
- SystemVerilog to Verilog conversion☆639Updated last month
- Verilog digital signal processing components☆143Updated 2 years ago
- Fabric generator and CAD tools.☆187Updated last week
- A git-friendly Vivado wrapper☆232Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- A simple RISC-V processor for use in FPGA designs.☆277Updated 10 months ago
- A simple, basic, formally verified UART controller☆304Updated last year
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆275Updated 5 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆329Updated 3 months ago
- Control and Status Register map generator for HDL projects☆116Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago