slaclab / surf

Related projects ⓘ

Alternatives and complementary repositories for surf

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆369Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆485Updated 9 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆225Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆513Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆265Updated 7 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆273Updated this week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆179Updated last year
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆550Updated 3 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆192Updated 2 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆363Updated this week
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆105Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆212Updated 11 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆557Updated 2 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆359Updated 3 weeks ago
• open-logic / open-logic
  Open Logic HDL Standard Library
  ☆340Updated this week
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆258Updated last year
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆403Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆282Updated 9 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆198Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆369Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆637Updated this week
• pyuvm / pyuvm
  The UVM written in Python
  ☆371Updated 3 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆295Updated this week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆363Updated 3 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆433Updated 2 weeks ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆562Updated this week
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆385Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆217Updated 5 months ago
• Xilinx / XilinxBoardStore
  ☆255Updated 2 weeks ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated this week