Alternatives and similar repositories for surf:

Users that are interested in surf are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆389Updated last month
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆236Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆183Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆159Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆575Updated 4 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆590Updated this week
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆201Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆244Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆373Updated last month
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆669Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆382Updated 2 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆315Updated 10 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆415Updated 2 months ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆272Updated 11 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆601Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆400Updated 6 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆280Updated last week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆550Updated this week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆230Updated 10 months ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆376Updated 2 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆426Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆294Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆276Updated 5 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆309Updated this week
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆431Updated last week
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆286Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆460Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆602Updated this week