Alternatives and similar repositories for surf

Users that are interested in surf are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆411Updated last month
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆186Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆602Updated 6 months ago
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆595Updated 3 months ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆191Updated 2 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆226Updated last month
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆251Updated last month
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆296Updated last month
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆459Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆312Updated last year
• rggen / rggen
  Code generation tool for control and status registers
  ☆428Updated last week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆240Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆263Updated last week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆127Updated 5 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆295Updated this week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆721Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆665Updated last month
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆202Updated last year
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆425Updated 2 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆390Updated 5 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆479Updated last week
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 5 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆672Updated 2 weeks ago
• Digilent / vivado-boards
  ☆468Updated 3 months ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆807Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆463Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆347Updated this week