Alternatives and similar repositories for surf:

Users that are interested in surf are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆394Updated 2 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆537Updated 2 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆237Updated 2 weeks ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆183Updated last year
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆577Updated 4 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆160Updated this week
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆675Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆599Updated 3 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆421Updated 2 weeks ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆422Updated 7 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆251Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆415Updated 7 months ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆204Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆519Updated last year
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆232Updated 10 months ago
• alexforencich / verilog-uart
  Verilog UART
  ☆468Updated last month
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆282Updated last week
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆434Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆298Updated last year
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆279Updated last year
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆275Updated 5 years ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆273Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆309Updated 3 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆613Updated last week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆572Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆379Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆387Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆312Updated this week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆565Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆768Updated 2 weeks ago