Alternatives and similar repositories for surf

Users that are interested in surf are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆414Updated this week
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆599Updated 4 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆609Updated 7 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆189Updated last week
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆252Updated last week
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆191Updated 2 years ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆230Updated 3 weeks ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆489Updated 3 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆298Updated 2 months ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆242Updated last year
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆454Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆297Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆364Updated 9 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆724Updated 2 weeks ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆469Updated 3 weeks ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆434Updated 3 weeks ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆278Updated last year
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆128Updated 6 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆677Updated 2 weeks ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆266Updated last week
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated last week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆674Updated 2 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆397Updated 2 months ago
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆821Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆427Updated 2 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆483Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆283Updated 6 years ago