slaclab / surfLinks
A huge VHDL library for FPGA and digital ASIC development
☆391Updated this week
Alternatives and similar repositories for surf
Users that are interested in surf are comparing it to the libraries listed below
Sorting:
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆402Updated 2 months ago
- OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...☆243Updated 3 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆172Updated 2 weeks ago
- Bus bridges and other odds and ends☆572Updated 3 months ago
- Flexible VHDL library☆187Updated 2 years ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆581Updated 4 years ago
- Style guide enforcement for VHDL☆211Updated this week
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆283Updated 3 weeks ago
- A simple, basic, formally verified UART controller☆306Updated last year
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆277Updated 5 years ago
- AXI interface modules for Cocotb☆270Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆625Updated 3 months ago
- Open Logic FPGA Standard Library☆671Updated 2 weeks ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆435Updated 10 months ago
- SPI Master for FPGA - VHDL and Verilog☆296Updated last year
- Code generation tool for control and status registers☆403Updated last month
- An abstraction library for interfacing EDA tools☆699Updated 3 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆290Updated last week
- Control and Status Register map generator for HDL projects☆118Updated last month
- HDL symbol generator☆190Updated 2 years ago
- SystemRDL 2.0 language compiler front-end☆255Updated last week
- A git-friendly Vivado wrapper☆235Updated last year
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆202Updated 8 months ago
- Verilog digital signal processing components☆143Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆492Updated 3 years ago
- Opensource DDR3 Controller☆362Updated last month
- The UVM written in Python☆440Updated this week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆338Updated 4 months ago
- Common SystemVerilog components☆634Updated this week