Alternatives and similar repositories for surf

Users that are interested in surf are comparing it to the libraries listed below

• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆399Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆560Updated last month
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆243Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆623Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆185Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆432Updated 8 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆690Updated 3 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆349Updated last year
• pyuvm / pyuvm
  The UVM written in Python
  ☆429Updated last month
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆261Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆288Updated this week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆236Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆429Updated 8 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆269Updated 4 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆333Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆630Updated 2 weeks ago
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆210Updated last month
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆389Updated 4 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆467Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 5 months ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆616Updated 3 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆798Updated 3 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆274Updated 9 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆329Updated 3 months ago