Alternatives and similar repositories for myhdl

Users that are interested in myhdl are comparing it to the libraries listed below

• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,293Updated last month
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,025Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,309Updated 3 weeks ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,309Updated last year
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆783Updated 2 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,473Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆725Updated last year
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,428Updated 5 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆720Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆675Updated 3 years ago
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆581Updated 4 years ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,117Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,078Updated last month
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,049Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,822Updated this week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆809Updated last month
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆966Updated last year
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆920Updated 2 weeks ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆701Updated last month
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,726Updated 2 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆669Updated 3 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆937Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,043Updated 5 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆3,918Updated this week
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆503Updated 2 years ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆845Updated 6 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆549Updated 3 months ago
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,817Updated last week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆652Updated 2 weeks ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,581Updated 2 weeks ago