Alternatives and similar repositories for myhdl

Users that are interested in myhdl are comparing it to the libraries listed below

• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,275Updated 3 weeks ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,410Updated 3 months ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,293Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆775Updated 3 weeks ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,063Updated 2 months ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,444Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆1,993Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,293Updated last year
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆579Updated 4 years ago
• nickg / nvc
  VHDL compiler and simulator
  ☆696Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆717Updated 11 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆803Updated 2 weeks ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆915Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆998Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,036Updated 3 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,589Updated 2 weeks ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆672Updated 3 years ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆538Updated 2 months ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,704Updated 2 weeks ago
• darklife / darkriscv
  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
  ☆2,328Updated last week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,064Updated this week
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,103Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆669Updated this week
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆399Updated 3 weeks ago
• YosysHQ / arachne-pnr
  Place and route tool for FPGAs
  ☆420Updated 5 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆690Updated 3 weeks ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,794Updated this week
• westerndigitalcorporation / swerv_eh1
  A directory of Western Digital’s RISC-V SweRV Cores
  ☆866Updated 5 years ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆833Updated 4 months ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆782Updated 3 weeks ago