Alternatives and similar repositories for myhdl

Users that are interested in myhdl are comparing it to the libraries listed below

• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated 3 weeks ago
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,384Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,248Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆812Updated 3 weeks ago
• nickg / nvc
  VHDL compiler and simulator
  ☆769Updated this week
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,124Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,394Updated last year
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,503Updated last month
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,602Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,127Updated 4 months ago
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆682Updated 4 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆747Updated last week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆767Updated last year
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆847Updated 7 months ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆1,003Updated last year
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆600Updated 6 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,193Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆681Updated 6 months ago
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,894Updated last week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,044Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,745Updated 3 weeks ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆570Updated 3 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆682Updated last month
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆423Updated last week
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,751Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆572Updated 5 months ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,340Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆995Updated 2 weeks ago
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆613Updated 7 years ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,103Updated 6 months ago