Alternatives and similar repositories for myhdl

Users that are interested in myhdl are comparing it to the libraries listed below

• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,308Updated last week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,101Updated last week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆792Updated 2 months ago
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,341Updated last year
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,344Updated this week
• nickg / nvc
  VHDL compiler and simulator
  ☆744Updated this week
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆594Updated 2 months ago
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,462Updated 2 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,149Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆679Updated 3 years ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,094Updated 3 weeks ago
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆753Updated last year
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,091Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,529Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,070Updated 3 months ago
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆977Updated last year
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆715Updated 3 weeks ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆672Updated 2 months ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,004Updated last week
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆828Updated 4 months ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆409Updated 2 weeks ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,190Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆553Updated last month
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆856Updated last week
• Obijuan / open-fpga-verilog-tutorial
  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
  ☆826Updated 5 years ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆430Updated last month
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆594Updated 7 years ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,857Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,120Updated 4 months ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,658Updated this week