Alternatives and similar repositories for myhdl

Users that are interested in myhdl are comparing it to the libraries listed below

• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,381Updated 3 weeks ago
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,218Updated this week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆807Updated last week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆765Updated last year
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,385Updated last year
• VLSI-EDA / PoC
  The PoC Library has been forked to github.com/VHDL/PoC. See new address below
  ☆600Updated 5 months ago
• nickg / nvc
  VHDL compiler and simulator
  ☆767Updated this week
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,496Updated last month
• pulp-platform / pulpino
  An open-source microcontroller system based on RISC-V
  ☆1,000Updated last year
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆737Updated 3 weeks ago
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆1,119Updated this week
• m-labs / nmigen
  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
  ☆681Updated 4 years ago
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,593Updated this week
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆678Updated 5 months ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,128Updated 3 months ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆845Updated 7 months ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,184Updated this week
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆570Updated 4 months ago
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,092Updated 5 months ago
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,903Updated this week
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆1,039Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,880Updated 3 weeks ago
• fabriziotappero / ip-cores
  A huge collection of VHDL/Verilog open-source IP cores scraped from the web
  ☆559Updated 2 years ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆419Updated 2 weeks ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆890Updated last week
• seldridge / verilog
  Repository for basic (and not so basic) Verilog blocks with high re-use potential
  ☆606Updated 7 years ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆439Updated 4 months ago
• KastnerRG / pp4fpgas
  Parallel Programming for FPGAs -- An open-source high-level synthesis book
  ☆870Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,726Updated last week