Alternatives and similar repositories for oss-cad-suite-build:

Users that are interested in oss-cad-suite-build are comparing it to the libraries listed below

• projf / projf-explore
  Project F brings FPGAs to life with exciting open-source designs you can build on.
  ☆633Updated 2 months ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,288Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,409Updated this week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,514Updated last week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,256Updated last week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆731Updated last week
• YosysHQ / apicula
  Project Apicula 🐝: bitstream documentation for Gowin FPGAs
  ☆543Updated this week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆376Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆604Updated this week
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,045Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆602Updated this week
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆972Updated 3 years ago
• lnis-uofu / OpenFPGA
  An Open-source FPGA IP Generator
  ☆887Updated this week
• stnolting / neorv32
  A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent …
  ☆1,709Updated this week
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆620Updated 2 weeks ago
• f4pga / prjxray
  Documenting the Xilinx 7-series bit-stream format.
  ☆791Updated last week
• JulianKemmerer / PipelineC
  A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler …
  ☆637Updated last week
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆421Updated 6 months ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆647Updated 4 months ago
• lowRISC / ibex
  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
  ☆1,494Updated last month
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆550Updated this week
• drom / awesome-hdl
  Hardware Description Languages
  ☆1,009Updated last month
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆401Updated 2 years ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆904Updated 4 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,028Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆435Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆526Updated last month
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,494Updated last month
• siliconcompiler / siliconcompiler
  Modular hardware build system
  ☆957Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆862Updated last year