Alternatives and similar repositories for wavedrom

Users that are interested in wavedrom are comparing it to the libraries listed below

• wavedrom / wavedrom.github.io
  Digital timing diagram editor
  ☆1,042Updated 10 months ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,487Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,175Updated this week
• nturley / netlistsvg
  draws an SVG schematic from a JSON netlist
  ☆751Updated last year
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,634Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,371Updated 2 weeks ago
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,705Updated 3 months ago
• wavedrom / bitfield
  bit field diagram renderer
  ☆382Updated last year
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,485Updated this week
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,569Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,927Updated this week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆875Updated last week
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,213Updated last week
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,704Updated last month
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,174Updated this week
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,267Updated this week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,939Updated this week
• amaranth-lang / amaranth
  A modern hardware definition language and toolchain based on Python
  ☆1,862Updated last week
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆677Updated this week
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,373Updated last year
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,830Updated last year
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,891Updated last week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,316Updated 2 months ago
• pConst / basic_verilog
  Must-have verilog systemverilog modules
  ☆1,888Updated 4 months ago
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,843Updated last week
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆803Updated this week
• steveicarus / iverilog
  Icarus Verilog
  ☆3,252Updated 2 weeks ago
• analogdevicesinc / hdl
  HDL libraries and projects
  ☆1,799Updated this week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,228Updated last year
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆928Updated this week