Alternatives and similar repositories for wavedrom

Users that are interested in wavedrom are comparing it to the libraries listed below

• wavedrom / wavedrom.github.io
  Digital timing diagram editor
  ☆1,057Updated 11 months ago
• trabucayre / openFPGALoader
  Universal utility for programming FPGA
  ☆1,529Updated this week
• FPGAwars / icestudio
  Visual editor for open FPGA boards
  ☆1,864Updated 3 weeks ago
• steveicarus / iverilog
  Icarus Verilog
  ☆3,297Updated this week
• nturley / netlistsvg
  draws an SVG schematic from a JSON netlist
  ☆760Updated 2 years ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,252Updated this week
• YosysHQ / picorv32
  PicoRV32 - A Size-Optimized RISC-V CPU
  ☆3,899Updated last year
• verilator / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆3,316Updated this week
• m-labs / migen
  A Python toolbox for building complex digital hardware
  ☆1,320Updated 3 weeks ago
• enjoy-digital / litex
  Build your hardware, easily!
  ☆3,692Updated last week
• SpinalHDL / VexRiscv
  A FPGA friendly 32 bit RISC-V CPU implementation
  ☆2,993Updated last month
• YosysHQ / nextpnr
  nextpnr portable FPGA place and route tool
  ☆1,598Updated this week
• stnolting / neorv32
  🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
  ☆1,969Updated this week
• cocotb / cocotb
  cocotb: Python-based chip (RTL) verification
  ☆2,231Updated this week
• SpinalHDL / SpinalHDL
  Scala based HDL
  ☆1,910Updated this week
• ghdl / ghdl
  VHDL 2008/93/87 simulator
  ☆2,739Updated last week
• hdl-util / hdmi
  Send video/audio over HDMI on an FPGA
  ☆1,243Updated last year
• aolofsson / oh
  Verilog library for ASIC and FPGA designers
  ☆1,392Updated last year
• FPGAwars / apio
  Open source ecosystem for open FPGA boards
  ☆947Updated this week
• olofk / fusesoc
  Package manager and build abstraction tool for FPGA/ASIC development
  ☆1,385Updated 2 weeks ago
• YosysHQ / oss-cad-suite-build
  Multi-platform nightly builds of open source digital design and verification tools
  ☆1,330Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,750Updated last month
• ZipCPU / zipcpu
  A small, light weight, RISC CPU soft core
  ☆1,502Updated last month
• myhdl / myhdl
  The MyHDL development repository
  ☆1,109Updated 9 months ago
• YosysHQ / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
  ☆1,128Updated 4 months ago
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆892Updated 2 weeks ago
• olofk / serv
  SERV - The SErial RISC-V CPU
  ☆1,740Updated 3 weeks ago
• Obijuan / open-fpga-verilog-tutorial
  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
  ☆844Updated 5 years ago
• VUnit / vunit
  VUnit is a unit testing framework for VHDL/SystemVerilog
  ☆812Updated 2 weeks ago
• wavedrom / bitfield
  bit field diagram renderer
  ☆386Updated last year